US 9,811,122 B2
Package on packages and mobile computing devices having the same
Heung Kyu Kwon, Seongnam-Si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Heung Kyu Kwon, Seongnam-Si (KR)
Filed on Dec. 1, 2015, as Appl. No. 14/955,281.
Claims priority of application No. 10-2014-0173629 (KR), filed on Dec. 5, 2014.
Prior Publication US 2016/0161992 A1, Jun. 9, 2016
Int. Cl. H01L 23/02 (2006.01); G06F 1/16 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 25/18 (2006.01)
CPC G06F 1/1658 (2013.01) [H01L 23/48 (2013.01); H01L 23/49811 (2013.01); H01L 23/5383 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 25/18 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48235 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92125 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A package on package, comprising:
a first printed circuit board (PCB);
a bottom package attached to the first PCB, the bottom package including a first chip die and a second chip die;
a top package over the bottom package, the top package including a second PCB, a third chip die, and a memory controller, the third chip die and the memory controller attached to the second PCB, the third chip die including a flash-based memory chip die, the memory controller configured to control operation of the third chip die; and
first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package,
wherein all signals and at least some of supply voltages for operations of the third chip die and the memory controller are transmitted through the first stack connection solder balls.