US 9,811,113 B2
System and method for synchronization among multiple PLL-based clock signals
Richard William Ezell, Lucas, TX (US); and Eric Wright Mumper, Plano, TX (US)
Assigned to Linear Technology Corporation, Milpitas, CA (US)
Filed by Linear Technology Corporation, Milpitas, CA (US)
Filed on Jul. 12, 2016, as Appl. No. 15/208,482.
Claims priority of provisional application 62/254,037, filed on Nov. 11, 2015.
Prior Publication US 2017/0134031 A1, May 11, 2017
Int. Cl. G06F 1/12 (2006.01); H03L 7/23 (2006.01); G06F 1/10 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/10 (2013.01); H03L 7/23 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A clock generation system receiving a reference frequency signal and a synchronization signal having a first logic state and a second logic state, comprising a plurality of clock generators connected in parallel to receive the reference frequency signal, wherein each clock generator comprises:
a reference frequency divider which receives the reference frequency signal and provides a frequency-divided reference signal;
a phase-locked loop which receives the frequency-divided reference signal and provides a phase-locked signal that is phase-locked to the frequency-divided reference signal; and
an output frequency divider that receives the phase-locked signal and provides an output signal of a predetermined frequency that is a function of the frequency of the reference frequency signal, wherein the reference frequency divider is phase-reset by a transition to the first logic state in the synchronization signal, and wherein the output frequency divider is phase-reset by a transition to the second logic state following the transition to the first logic state in the synchronization signal.