US 9,811,112 B2
Adaptive clock delay compensation
Subrahmanya Bharathi Akondy, Houston, TX (US); and Steven Brett Larimore, Houston, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 18, 2016, as Appl. No. 14/997,862.
Prior Publication US 2017/0205845 A1, Jul. 20, 2017
Int. Cl. G06F 1/12 (2006.01)
CPC G06F 1/12 (2013.01) 17 Claims
OG exemplary drawing
 
16. A method, comprising:
generating a clock edge of a clock having a first frequency;
detecting a subsequent data edge;
counting clock cycles of a counter clock between the clock and data edges to produce a first delay value;
converting the delay value to a second delay value based, at least in part, on a second frequency, wherein the second frequency is different than the first frequency;
writing the second delay value to a register;
generating a first clock at the second frequency;
generating a second clock at the second frequency delayed from the first clock by the second delay value;
transmitting the first clock to a remote device and the second clock to the data interface; and
performing a data transfer operation between a remote device and a data interface using a clock having the second frequency.