US 9,811,107 B2
Low power bias current generator and voltage reference
Stefan Marinca, Limerick City (IE)
Assigned to Analog Devices Global, Hamilton (BM)
Filed by Analog Devices Global, Hamilton (BM)
Filed on Jul. 1, 2015, as Appl. No. 14/789,477.
Prior Publication US 2017/0003704 A1, Jan. 5, 2017
Int. Cl. G05F 1/10 (2006.01); G05F 3/26 (2006.01)
CPC G05F 3/267 (2013.01) 22 Claims
OG exemplary drawing
1. A bias current generator comprising:
a first bipolar transistor and a second bipolar transistor, the second bipolar transistor configured to operate with a different collector current density than the first bipolar transistor to generate a ΔVBE voltage that is a difference in base-emitter voltages of the first and second bipolar transistors;
a plurality of stacked metal oxide semiconductor (MOS) devices biased in a transistor triode operating region and operatively coupled to the first and second bipolar transistors to generate a reference bias current determined by the ΔVBE voltage and an on resistance of the stacked MOS devices;
a biasing MOS device, wherein the plurality of stacked MOS devices have a common source/drain connection coupled to a source/drain of the biasing MOS device and wherein a drain voltage of each of the biasing MOS device and the stacked MOS devices is determined by the ΔVBE voltage; and
a plurality of current mirrors and an amplifier, wherein the stacked MOS devices are coupled between the current mirrors and inputs of an amplifier, the stacked MOS devices comprising a first MOS device coupled to a first input of the amplifier and a second MOS device coupled to a second input of the amplifier.