US 9,811,056 B2
High resolution time-to-digital convertor
Lan-Chou Cho, Hsin-Chu (TW); Chewn-Pu Jou, Hsin-Chu (TW); Feng-Wei Kuo, Hsin-Chu (TW); and Huan-Neng Chen, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsin-Chu (TW)
Filed on Feb. 2, 2017, as Appl. No. 15/422,523.
Application 15/422,523 is a division of application No. 14/689,096, filed on Apr. 17, 2015, granted, now 9,571,082.
Prior Publication US 2017/0146959 A1, May 25, 2017
Int. Cl. H03M 1/50 (2006.01); G04F 10/00 (2006.01); H03K 5/1534 (2006.01); H03K 5/131 (2014.01); H03K 5/00 (2006.01)
CPC G04F 10/005 (2013.01) [H03K 5/131 (2013.01); H03K 5/1534 (2013.01); H03K 2005/00058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a pulse generator configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal;
a spatial division multiplexing circuit configured to receive the delta pulse signal and the reference clock signal and generate an output indicative of a time difference between the input clock signal and the reference clock signal; and
a counter configured to maintain a count representing the time difference between the input clock signal and the reference clock signal.