US 9,810,843 B2
Optical backplane mirror
Tab A. Stephens, Austin, TX (US); Perry H. Pelley, Austin, TX (US); and Michael B. McShane, Austin, TX (US)
Assigned to NXP USA, INC., Austin, TX (US)
Filed by Freescale Semiconductor, Inc., Austin, TX (US)
Filed on Jun. 10, 2013, as Appl. No. 13/914,178.
Prior Publication US 2014/0363120 A1, Dec. 11, 2014
Int. Cl. G02B 6/12 (2006.01); G02B 6/136 (2006.01); G02B 6/13 (2006.01); G02B 6/125 (2006.01); G02B 6/43 (2006.01); G02B 6/42 (2006.01)
CPC G02B 6/136 (2013.01) [G02B 6/125 (2013.01); G02B 6/131 (2013.01); G02B 6/43 (2013.01); G02B 6/4214 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12104 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor fabrication process comprising:
providing a wafer comprising an optical waveguide semiconductor structure;
selectively etching the optical waveguide semiconductor structure with an anisotropic wet etch process to form an angled semiconductor sidewall surface on the optical waveguide semiconductor structure; and
processing the angled semiconductor sidewall surface on the optical waveguide semiconductor structure to form a mirror for deflecting optical signals into and out of a lateral plane that is parallel to a major wafer substrate surface,
where the wafer comprises a semiconductor-on-insulator (SOI) substrate with an optical through-semiconductor via structure formed in the SOI substrate in optical alignment with the mirror.