US 9,810,740 B2
DAP local, group, and global control of TAP TCK
Lee D. Whetsel, Parker, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 12, 2016, as Appl. No. 15/235,912.
Application 15/235,912 is a division of application No. 14/698,298, filed on Apr. 28, 2015, granted, now 9,442,162.
Application 14/698,298 is a division of application No. 13/596,889, filed on Aug. 28, 2012, granted, now 9,046,575, issued on Jun. 2, 2015.
Application 13/596,889 is a division of application No. 13/238,736, filed on Sep. 21, 2011, granted, now 8,281,196, issued on Oct. 2, 2012.
Application 13/238,736 is a division of application No. 12/401,028, filed on Mar. 10, 2009, granted, now 8,046,650, issued on Oct. 25, 2011.
Claims priority of provisional application 61/036,686, filed on Mar. 14, 2008.
Prior Publication US 2016/0349324 A1, Dec. 1, 2016
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31723 (2013.01); G01R 31/31727 (2013.01); G01R 31/318555 (2013.01); G01R 31/318572 (2013.01)] 4 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
(a) a test data input lead, a test clock lead, a test mode select lead, and a test data output lead;
(b) test access port circuitry including:
(i) a TAP state machine having a test clock input connected to the test clock lead, a test mode select input, and control outputs;
(ii) an instruction register having a test data input connected to the test data in lead, a test data output, control inputs connected to the control outputs, and instruction outputs;
(iii) a data register having a test data input connected to the test data in lead, a test data output, and control inputs connected to the control outputs;
(iv) multiplexer circuitry coupling the test data outputs of the instruction register and the data register to the test data out lead; and
(v) control circuitry having an input connected to the test clock lead, having a local control input, a group control input, and a global TAP control input, and an output connected to the test clock input of the state machine; and
(c) device address port circuitry having a test clock input coupled to the test clock lead, a test mode select input connected to the test mode select lead, a test data input connected to the test data input lead, and local, group, and global TAP control outputs connected to the respective local, group, and global TAP control inputs.