US 9,810,738 B2
Semiconductor device, diagnostic test, and diagnostic test circuit
Yukitoshi Tsuboi, Kawasaki (JP); Hideo Nagano, Kawasaki (JP); Hiroshi Nagaoka, Kawasaki (JP); Yusuke Matsunaga, Kawasaki (JP); Yutaka Igaku, Kawasaki (JP); and Naotaka Kubota, Kawasaki (JP)
Assigned to Renesas Electronics Corporation, Kawasaki-shi, Kanagawa (JP)
Filed by Renesas Electronics Corporation, Kawasaki-shi (JP)
Filed on Apr. 1, 2015, as Appl. No. 14/676,743.
Claims priority of application No. 2014-081852 (JP), filed on Apr. 11, 2014; and application No. 2015-016443 (JP), filed on Jan. 30, 2015.
Prior Publication US 2015/0293173 A1, Oct. 15, 2015
Int. Cl. G11C 29/00 (2006.01); G06F 11/00 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G06F 11/08 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/318544 (2013.01); G06F 11/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of CPU (Central Processing Unit) cores each comprising a scan chain; and
a diagnostic test circuit that performs a scan test for the plurality of CPU cores by using the scan chain in each of the CPU cores, wherein
the diagnostic test circuit performs a scan test for each of the plurality of CPU cores in a predetermined order so that execution time periods of the scan tests do not overlap each other,
the scan test for each of the plurality of CPU cores is repeated periodically until the diagnostic test circuit determines that there is a failure in the plurality of CPU cores, and
during an execution time period of the scan test for one of the plurality of CPU cores, the rest of the plurality of CPU cores perform normal operations.