US 9,810,737 B2
Gating tap register control bus and auxiliary/wrapper test bus
Lee D. Whetsel, Parker, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 22, 2016, as Appl. No. 15/359,073.
Application 15/359,073 is a division of application No. 15/089,988, filed on Apr. 4, 2016, granted, now 9,535,124.
Application 15/089,988 is a division of application No. 14/800,276, filed on Jul. 15, 2015, granted, now 9,329,233, issued on May 3, 2016.
Application 14/800,276 is a division of application No. 14/546,722, filed on Nov. 18, 2014, granted, now 9,116,209, issued on Aug. 25, 2015.
Application 14/546,722 is a division of application No. 14/085,072, filed on Nov. 20, 2013, granted, now 8,918,688, issued on Dec. 23, 2014.
Application 14/085,072 is a division of application No. 13/782,540, filed on Mar. 1, 2013, granted, now 8,621,299, issued on Dec. 31, 2013.
Application 13/782,540 is a division of application No. 13/551,080, filed on Jul. 17, 2012, granted, now 8,412,992, issued on Apr. 2, 2013.
Application 13/551,080 is a division of application No. 13/289,577, filed on Nov. 4, 2011, granted, now 8,250,419, issued on Aug. 21, 2012.
Application 13/289,577 is a division of application No. 12/791,133, filed on Jun. 1, 2010, granted, now 8,078,927, issued on Dec. 13, 2011.
Application 12/791,133 is a division of application No. 12/165,928, filed on Jul. 1, 2008, abandoned.
Application 12/165,928 is a division of application No. 10/874,054, filed on Jun. 21, 2004, granted, now 7,409,611, issued on Aug. 5, 2008.
Claims priority of provisional application 60/483,437, filed on Jun. 27, 2003.
Prior Publication US 2017/0074936 A1, Mar. 16, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G06F 17/50 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/31723 (2013.01) [G01R 31/3177 (2013.01); G01R 31/31724 (2013.01); G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/318508 (2013.01); G01R 31/318536 (2013.01); G06F 17/5081 (2013.01)] 4 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
A. a TDI lead, a TDO lead, a TMS lead, and a TCK lead;
B. a test access port controller having inputs connected to the TMS and TCK leads and having a ClockDR output, a ShiftDR output, and an UpdateDR output;
C. instruction register circuitry having a Mode-1 output and an ATC enable output, the instruction register circuitry including a first gate with a ClockDR input connected to the ClockDR output and a Clock-1 output, and a second gate with a gated UpdateDR input and an Update-1 output;
D. data register circuitry having a TDI input connected to the TDI lead, a TDO output selectively coupled to the TDO lead, a Mode-1 input connected to the Mode-1 output, a Clock-1 input connected to the Clock-1 output, a Shift-1 input, and an Update-1 input connected to the Update-1 output; and
E. ATC gating circuitry having an ATC enable input connected to the ATC enable output, a ShiftDR input connected to the ShiftDR output, a Capture input, a Shift-1 output connected to the Shift-1 input, an UpdateDR input connected to the UpdateDR output, an Update input, and a gated UpdateDR output connected to the gated UpdateDR input.