US 9,810,736 B2
System and apparatus for trusted and secure test ports of integrated circuit devices
Rodrick Cottrell, Fort Wayne, IN (US); and Dee C. Neuenschwander, Fort Wayne, IN (US)
Assigned to Raytheon Company, Waltham, MA (US)
Filed by Raytheon Company, Waltham, MA (US)
Filed on Dec. 17, 2015, as Appl. No. 14/972,990.
Prior Publication US 2017/0176530 A1, Jun. 22, 2017
Int. Cl. G01R 31/00 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/31719 (2013.01) [G01R 31/3177 (2013.01)] 19 Claims
OG exemplary drawing
15. A method for securing JTAG scan chains, comprising:
separately coupling a plurality of JTAG enabled devices in the JTAG scan chains to a secure trusted boot device;
detecting JTAG security events by the trusted boot device; and
decoupling one or more JTAG paths between the JTAG enabled devices and the trusted boot device while the JTAG paths are configured in an initial unsecure state.