US 9,810,729 B2
Tester with acceleration for packet building within a FPGA block
John Frediani, Corralitos, CA (US)
Filed by Advantest Corporation, Tokyo (JP)
Filed on Feb. 28, 2013, as Appl. No. 13/781,337.
Prior Publication US 2014/0244204 A1, Aug. 28, 2014
Int. Cl. G01R 27/28 (2006.01); G01R 31/00 (2006.01); G01R 31/14 (2006.01); G01R 31/319 (2006.01)
CPC G01R 31/00 (2013.01) [G01R 31/31907 (2013.01)] 20 Claims
OG exemplary drawing
20. A tester system comprising:
a system controller communicatively coupled to a tester processor, wherein said system controller is operable to control a test program;
an instantiated FPGA block communicatively coupled to said tester processor, wherein said instantiated FPGA block comprises:
a reconfigurable protocol engine circuit operable to communicate with a DUT using a high speed communication protocol particular to said DUT; and
a packet builder circuit operable to generate packets comprising commands and data for running test operations on said DUT, wherein said DUT is coupled to said instantiated FPGA block, and further wherein said packets are communicated to said DUT using said high speed communication protocol,
wherein said reconfigurable protocol engine circuit and said packet builder circuit are programmed onto said instantiated FPGA block using said tester processor.