US 9,810,584 B2
Temperature sensor with layered architecture
Jukka Kohola, Oulu (FI); and Marko Pessa, Oulu (FI)
Assigned to OPTIS CIRCUIT TECHNOLOGY, LLC, Plano, TX (US)
Appl. No. 14/763,613
Filed by Optis Circuit Technology, LLC, Plano, TX (US)
PCT Filed Feb. 10, 2014, PCT No. PCT/EP2014/052560
§ 371(c)(1), (2) Date Jul. 27, 2015,
PCT Pub. No. WO2014/131607, PCT Pub. Date Sep. 4, 2014.
Claims priority of provisional application 61/815,034, filed on Apr. 23, 2013.
Claims priority of application No. 13156870 (EP), filed on Feb. 27, 2013.
Prior Publication US 2015/0362380 A1, Dec. 17, 2015
Int. Cl. G01K 7/00 (2006.01); G01K 7/01 (2006.01); G05F 3/30 (2006.01)
CPC G01K 7/01 (2013.01) [G01K 7/015 (2013.01); G05F 3/30 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A temperature sensor comprising: two branches, each branch including at least a first transistor and a second transistor connected as diodes and cascaded so that an emitter of the first transistor of a first layer of a branch is connected to a collector of the second transistor of a second layer of the same branch a current source configured to provide a current to the two branches; and an analog-to-digital convertor connected to capture a voltage between emitters of the first transistors or of the second transistors, and configured to convert said voltage to a digital temperature signal, wherein the first and the second transistor of a first branch among the two branches have a same first PN-junction area and a first and a second transistor of a second branch among the two branches have a same second PN-junction area, said second PN-junction area being different from said first PN-junction area by a predetermined factor.