Class 326: ELECTRONIC DIGITAL LOGIC CIRCUITRY ( Manual of U.S. Patent Classification )

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Manual of U.S. Patent Classification
as of June 30, 2000


Class
326
ELECTRONIC DIGITAL LOGIC CIRCUITRY


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Subclass Title
ClassTitle ===> ELECTRONIC DIGITAL LOGIC CIRCUITRY
1[Patents]SUPERCONDUCTOR (E.G., CRYOGENIC, ETC.)
2[Patents] . Tunneling device
3[Patents] . . Josephson tunneling device
4[Patents] . . . Plural devices (e.g., distributive device, etc.)
5[Patents] . . . Interference device (i.e., SQUID)
6[Patents] . . Function of AND, OR, NAND, NOR, or NOT
7[Patents] . Function of AND, OR, NAND, NOR, or NOT
8[Patents]SECURITY (E.G., ACCESS OR COPY PREVENTION, ETC.)
9[Patents]RELIABILITY
10[Patents] . Redundant
11[Patents] . . Voter circuit (e.g., majority logic, etc.)
12[Patents] . . With flip-flop
13[Patents] . . With field effect-transistor
14[Patents] . Fail-safe
15[Patents] . Parasitic prevention in integrated circuit structure
16[Patents]WITH TEST FACILITATING FEATURE
17[Patents]ACCELERATING SWITCHING
18[Patents] . Bipolar transistor
19[Patents] . . With Schottky device
20[Patents] . . . Complementary transistors
21[Patents]SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY
22[Patents] . Input noise margin enhancement
23[Patents] . . With field effect-transistor
24[Patents] . . . Complementary FET`s
25[Patents] . . . Depletion or enhancement
26[Patents] . Output switching noise reduction
27[Patents] . . With field effect-transistor
28[Patents] . . . With clocking
29[Patents] . Pulse shaping (e.g., squaring, etc.)
30[Patents] . Bus or line termination (e.g., clamping, impedance matching, etc.)
31[Patents] . Signal level or switching threshold stabilization
32[Patents] . . Temperature compensation
33[Patents] . . Bias or power supply level stabilization
34[Patents] . . With field effect-transistor
35[Patents]THRESHOLD (E.G., MAJORITY, MINORITY, OR WEIGHTED INPUTS, ETC.)
36[Patents] . With field effect-transistor
37[Patents]MULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.)
38[Patents] . Having details of setting or programming of interconnections or logic functions
39[Patents] . Array (e.g., PLA, PAL, PLD, etc.)
40[Patents] . . With flip-flop or sequential device
41[Patents] . . Significant integrated structure, layout, or layout interconnections
42[Patents] . . Bipolar transistor
43[Patents] . . . Emitter-coupled logic or emitter-follower logic
44[Patents] . . Field effect transistor
45[Patents] . . . Complementary FET`s
46[Patents] . Sequential (i.e., finite state machine) or with flip-flop
47[Patents] . Significant integrated structure, layout, or layout interconnections
48[Patents] . Bipolar transistor
49[Patents] . Field-effect transistor
50[Patents] . . Complementary FET`s
51[Patents]INHIBITOR
52[Patents]EXCLUSIVE FUNCTION (E.G., EXCLUSIVE OR, ETC.)
53[Patents] . Half-adder or quarter-adder
54[Patents] . Exclusive NOR
55[Patents] . With field-effect transistor
56[Patents]TRI-STATE (I.E., HIGH IMPEDANCE AS THIRD STATE)
57[Patents] . With field effect-transistor
58[Patents] . . Complementary FET`s
59[Patents]THREE OR MORE ACTIVE LEVELS (E.G., TERNARY, QUATENARY, ETC.)
60[Patents] . With conversion (e.g., three level to two level, etc.)
61[Patents]INSULATED GATE CHARGE TRANSFER DEVICE
62[Patents]INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.)
63[Patents] . Logic level shifting (i.e., interface between devices of different logic families)
64[Patents] . . Bi-CMOS
65[Patents] . . . TTL to/from CMOS
66[Patents] . . . ECL to/from CMOS
67[Patents] . . . ECL to/from TTL
68[Patents] . . Field-effect transistor (e.g., JFET, MOSFET, etc.)
69[Patents] . . . ECL to/from GaAs FET (e.g., MESFET, etc.)
70[Patents] . . . TTL to/from MOS
71[Patents] . . . . TTL to/from CMOS
72[Patents] . . . . . Using depletion or enhancement transistors
73[Patents] . . . ECL to/from MOS
74[Patents] . . . ECL to/from TTL
75[Patents] . . Bipolar transistor
76[Patents] . . . TTL to/from MOS
77[Patents] . . . ECL to/from MOS
78[Patents] . . . ECL to/from TTL
79[Patents] . . . Integrated Injection Logic (I2L)
80[Patents] . Supply voltage level shifting (i.e., interface between devices of a same logic family with different operating voltage levels)
81[Patents] . . CMOS
82[Patents] . Current driving (e.g., fan in/out, off chip driving, etc.)
83[Patents] . . Field-effect transistor
84[Patents] . . . Bi-CMOS
85[Patents] . . . . Having plural output pull-up or pull-down transistors
86[Patents] . . . Bus driving
87[Patents] . . . Having plural output pull-up or pull-down transistors
88[Patents] . . . With capacitive or inductive bootstrapping
89[Patents] . . Bipolar transistor
90[Patents] . . . Bus driving
91[Patents] . . . Having plural output pull-up or pull-down transistors
92[Patents] . . . With capacitive or inductive bootstrapping
93[Patents]CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES
94[Patents] . Metastable state prevention
95[Patents] . Field-effect transistor
96[Patents] . . Two or more clocks (e.g., phase clocking, etc.)
97[Patents] . . . MOSFET
98[Patents] . . MOSFET
99[Patents]HAVING LOGIC LEVELS CONVEYED BY SIGNAL FREQUENCY OR PHASE
100[Patents]INTEGRATED INJECTION LOGIC
101[Patents]SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS
102[Patents] . Field-effect transistor
103[Patents] . . Complementary FET`s
104[Patents]FUNCTION OF AND, OR, NAND, NOR, or NOT
105[Patents] . Decoding
106[Patents] . . With field-effect transistor
107[Patents] . . . Depletion or enhancement
108[Patents] . . . CMOS
109[Patents] . Bipolar and FET
110[Patents] . . Bi-CMOS
111[Patents] . Space discharge device (e.g., vacuum tube, etc.)
112[Patents] . Field-effect transistor (e.g., JFET, etc.)
113[Patents] . . Pass transistor logic or transmission gate logic
114[Patents] . . Wired logic (e.g., wired-OR, wired-AND, dotted logic, etc.)
115[Patents] . . Source-coupled logic (e.g., current mode logic (CML), differential current switch logic (DCSL), etc.)
116[Patents] . . Schottky-gate FET (i.e., MESFET)
117[Patents] . . . Depletion or enhancement
118[Patents] . . . Diode transistor logic
119[Patents] . . MOSFET (i.e., metal-oxide semiconductor field-effect transistor)
120[Patents] . . . Depletion or enhancement
121[Patents] . . . CMOS
122[Patents] . . Complementary FET`s
123[Patents] . . With semiconductor diode or negative resistance device
124[Patents] . Bipolar transistor (e.g., RTL, DCTL, etc.)
125[Patents] . . Wired logic or open collector logic (e.g., wired-OR, wired-AND, dotted logic, etc.)
126[Patents] . . Emitter-coupled or emitter-follower logic
127[Patents] . . . Current mode logic (CML)
128[Patents] . . Transistor-transistor logic (TTL)
129[Patents] . . . Complementary transistor logic (CTL)
130[Patents] . . Diode-transistor logic (DTL)
131[Patents] . . . With metal semiconductor junction diode (e.g., Schottky barrier, etc.)
132[Patents] . . With negative resistance device (e.g., tunnel diode, thyristor, etc.)
133[Patents] . Diode
134[Patents] . . Negative resistance diode (e.g., tunnel, gunn, etc.)
135[Patents] . Negative resistance device
136[Patents]MISCELLANEOUS


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Last Modified: 6 October 2000