Manual of U.S. Patent Classification
as of June 30, 2000

Class
257
ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

Class definitions may be accessed by clicking on the class title, above.
Subclass definitions may be accessed by clicking on the subclass number, below.

Patents classified in a subclass may be accessed by clicking on the " " icon following the subclass number, below.

( please note that links to definitions and classified patents may not be available for some classes and subclasses )

For search strategies, please refer to the Classification Index Explanation of Data web page.

Subclass		Title
ClassTitle		===> ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)
1		BULK EFFECT DEVICE
2		. Bulk effect switching in amorphous material
3		. . With means to localize region of conduction (e.g., "pore" structure)
4		. . With specified electrode composition or configuration
5		. . In array
6		. Intervalley transfer (e.g., Gunn effect)
7		. . In monolithic integrated circuit
8		. . Three or more terminal device
9		THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE, QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE)
10		. Low workfunction layer for electron emission, e.g., photocathode electron emissive layer
11		. . Combined with a heterojunction involving a III-V compound
12		. Heterojunction
13		. . Incoherent light emitter
14		. . Quantum well
15		. . . Superlattice
16		. . . . Of amorphous semiconductor material
17		. . . . With particular barrier dimension
18		. . . . Strained layer superlattice
19		. . . . . Si Ge
20		. . . . Field effect device
21		. . . . Light responsive structure
22		. . . . With specified semiconductor materials
23		. . . Current flow across well
24		. . . Field effect device
25		. . . Employing resonant tunneling
26		. . Ballistic transport device
27		. . . Field effect transistor
28		. Non-heterojunction superlattice (e.g., doping superlattice or alternating metal and insulator layers)
29		. Ballistic transport device (e.g., hot electron transistor)
30		. Tunneling through region of reduced conductivity
31		. . Josephson
32		. . . Particular electrode material
33		. . . . High temperature (i.e., >30 Kelvin)
34		. . . Weak link (e.g., narrowed portion of superconductive line)
35		. . . Particular barrier material
36		. . . With additional electrode to control conductive state of Josephson junction
37		. . At least one electrode layer of semiconductor material
38		. . . Three or more electrode device
39		. . Three or more electrode device
40		ORGANIC SEMICONDUCTOR MATERIAL
41		POINT CONTACT DEVICE
42		SEMICONDUCTOR IS SELENIUM OR TELLURIUM IN ELEMENTAL FORM
43		SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CuO, ZnO) OR COPPER SULFIDE
44		WITH METAL CONTACT ALLOYED TO ELEMENTAL SEMICONDUCTOR TYPE PN JUNCTION IN NONREGENERATIVE STRUCTURE
45		. Elongated alloyed region (e.g., thermal gradient zone melting, TGZM)
46		. In pn junction tunnel diode (Esaki diode)
47		. In bipolar transistor structure
48		TEST OR CALIBRATION STRUCTURE
49		NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION)
50		. Non-single crystal, or recrystallized, active junction adapted to be electrically shorted (e.g., "anti-fuse" element)
51		. Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction)
52		. Amorphous semiconductor material
53		. . Responsive to nonelectrical external signals (e.g., light)
54		. . . With Schottky barrier to amorphous material
55		. . . Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si Ge , SiN )
56		. . . With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
57		. . Field effect device in amorphous semiconductor material
58		. . . With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
59		. . . In array having structure for use as imager or display, or with transparent electrode
60		. . . With field electrode under or on a side edge of amorphous semiconductor material (e.g., vertical current path)
61		. . . With heavily doped regions contacting amorphous semiconductor material (e.g., heavily doped source and drain)
62		. . With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
63		. . Amorphous semiconductor is alloy or contains material to change band gap (e.g., SixGe1-x, SiNy)
64		. Non-single crystal, or recrystallized, material with specified crystal structure (e.g., specified crystal size or orientation)
65		. Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., GexSi1-x, polycrystalline silicon with dangling bond modifier)
66		. Field effect device in non-single crystal, or recrystallized, semiconductor material
67		. . In combination with device formed in single crystal semiconductor material (e.g., stacked FETs)
68		. . . Capacitor element in single crystal semiconductor (e.g., DRAM)
69		. . . Field effect transistor in single crystal material, complememtary to that in non-single crystal, or recrystallized, material (e.g., CMOS)
70		. . . Recrystallized semiconductor material
71		. . In combination with capacitor element (e.g., DRAM)
72		. . In array having structure for use as imager or display, or with transparent electrode
73		. Schottky barrier to polycrystalline semiconductor material
74		. Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit")
75		. Recrystallized semiconductor material
76		SPECIFIED WIDE BAND GAP (> 1.5eV) SEMICONDUCTOR MATERIAL OTHER THAN GaAsP OR GaAlAs
77		. Diamond or Silicon Carbide
78		. II-IV compound
79		INCOHERENT LIGHT EMITTER STRUCTURE
80		. In combination with or also constituting light responsive device
81		. . With specific housing or contact structure
82		. . . Discrete light emitting and light responsive devices
83		. . Light coupled transistor structure
84		. . Combined in integrated structure
85		. . . With heterojunction
86		. Active layer of indirect band gap semiconductor
87		. . With means to facilitate electron-hole recombination (e.g., isoelectronic traps such as nitrogen in GaP)
88		. Plural light emitting devices (e.g., matrix, 7-segment array)
89		. . Multi-color emission
90		. . . With heterojunction
91		. . With shaped contacts or opaque masking
92		. . Alphanumeric segmented array
93		. . With electrical isolation means in integrated circuit structure
94		. With heterojunction
95		. . With contoured external surface (e.g., dome shape to facilitate light emission)
96		. . Plural heterojunctions in same device
97		. . . More than two heterojunctions in same device
98		. With reflector, opaque mask, or optical element (e.g., lens, optical fiber, index of refraction matching layer, luminescent material layer, filter) integral with device or device enclosure or package
99		. With housing or contact structure
100		. Encapsulated
101		. With particular dopant concentration or concentration profile (e.g., graded junction)
102		. With particular dopant material (e.g., Zinc as dopant in GaAs)
103		. With particular semiconductor material
104		TUNNELING PN JUNCTION (E.G., ESAKI DIODE) DEVICE
105		. In three or more terminal device
106		. Reverse bias tunneling structure (e.g., "backward" diode, true Zener diode)
107		REGENERATIVE TYPE SWITCHING DEVICE (E.G., SCR, COMFET, THYRISTOR)
108		. Controlled by nonelectrical, nonoptical external signal (e.g., magnetic field, pressure, thermal)
109		. Having only two terminals and no control electrode (gate) (e.g., Shockley diode)
110		. . More than four semiconductor layers of alternating conductivity types (e.g., pnpnpn structure, 5 layer bidirectional diacs, etc.)
111		. . Triggered by VBO overvoltage means
112		. . With highly-doped breakdown diode trigger
113		. With light activation
114		. . With separate light dector integrated on chip with regenerative switching device
115		. . With electrical trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.)
116		. . With light conductor means (e.g., light fiber or light pipe) integral with device or device enclosure or package
117		. . . In groove or with thinned semiconductor portion
118		. . With groove or thinned light sensitive portion
119		. Bidirectional rectifier with control electrode (gate) (e.g., Triac)
120		. . Six or more semiconductor layers of alternating conductivity types (e.g., npnpnpn structure)
121		. . With diode or transistor in reverse path
122		. . Lateral
123		. . With trigger signal amplification (e.g., amplified gate)
124		. . Combined with field effect transistor structure
125		. . . Controllable emitter shunting
126		. . With means to separate a device into sections having different conductive polarity
127		. . . Guard ring or groove
128		. . Having overlapping sections of different conductive polarity
129		. . With means to increase reverse breakdown voltage
130		. . Switching speed enhancement means
131		. . . Recombination centers or deep level dopants
132		. Five or more layer unidirectional structure
133		. Combined with field effect transistor
134		. . J-FET (junction field effect transistor)
135		. . . Vertical (i.e., where the source is located above the drain or vice versa)
136		. . . . Enhancement mode (e.g., so-called SITs)
137		. . Having controllable emitter shunt
138		. . . Having gate turn off (GTO) feature
139		. . With extended latchup current level (e.g., COMFET device)
140		. . . Combined with other solid state active device in integrated structure
141		. . . Lateral structure, i.e., current flow parallel to main device surface
142		. . . Having impurity doping for gain reduction
143		. . . Having anode shunt means
144		. . . Cathode emitter or cathode electrode feature
145		. . . Low impedance channel contact extends below surface
146		. Combined with other solid state active device in integrated structure
147		. With extended latchup current level (e.g., gate turn off "GTO" device)
148		. . Having impurity doping for gain reduction
149		. . Having anode shunt means
150		. . With specified housing or external terminal
151		. . . External gate terminal structure or composition
152		. . Cathode emitter or cathode electrode feature
153		. . Gate region or electrode feature
154		. With resistive region connecting separate sections of device
155		. With switching speed enhancement means (e.g., Schottky contact)
156		. . Having deep level dopants or recombination centers
157		. With integrated trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.)
158		. . Three or more amplification stages
159		. . Transistor as amplifier
160		. . With distributed amplified current
161		. . With a turn-off diode
162		. Lateral structure
163		. Emitter region feature
164		. . Multi-emitter region (e.g., emitter geometry or emitter ballast resistor)
165		. . . Laterally symmetric regions
166		. . . Radially symmetric regions
167		. Having at least four external electrodes
168		. With means to increase breakdown voltage
169		. . High resistivity base layer
170		. . Surface feature (e.g., guard ring, groove, mesa)
171		. . . Edge feature (e.g., beveled edge)
172		. With means to lower "ON" voltage drop
173		. Device protection (e.g., from overvoltage)
174		. . Rate of rise of current (e.g., dI/dt)
175		. With means to control triggering (e.g., gate electrode configuration, zener diode firing, dV/dt control, transient control by ferrite bead, etc.)
176		. . Located in an emitter-gate region
177		. With housing or external electrode
178		. . With means to avoid stress between electrode and active device (e.g., thermal expansion matching of electrode to semiconductor)
179		. . . With malleable electrode (e.g., silver electrode layer)
180		. . Stud mount
181		. . With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element (e.g., ring)
182		. . . With lead feedthrough means on side of housing
183		HETEROJUNCTION DEVICE
183.1		. Charge transfer device
184		. Light responsive structure
185		. . Staircase (including graded composition) device
186		. . Avalanche photodetection structure
187		. . Having transistor structure
188		. . Having narrow energy band gap (<<1eV) layer (e.g., PbSnTe, HgCdTe, etc.)
189		. . . Layer is a group III-V semiconductor compound
190		. With lattice constant mismatch (e.g., with buffer layer to accomodate mismatch)
191		. Having graded composition
192		. Field effect transistor
194		. . Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT)
195		. . . Combined with diverse type device
196		. Both semiconductors of the heterojunction are the same conductivity type (i.e., either N or P)
197		. Bipolar transistor
198		. . Wide band gap emitter
199		. Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts, including heterojunction IMPATT type microwave diodes)
200		. Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI))
201		. Between different group IV-VI or II-VI or III-V compounds other than GaAs/GaAlAs
202		GATE ARRAYS
203		. With particular chip input/output means
204		. Having specific type of active device (e.g., CMOS)
205		. . With bipolar transistors or with FETs of only one channel conductivity type (e.g., enhancement-depletion FETs)
206		. . Particular layout of complementary FETs with regard to each other
207		. With particular power supply distribution means
208		. With particular signal path connections
209		. . Programmable signal paths (e.g., with fuse elements, laser programmable, etc.)
210		. . With wiring channel area
211		. . Multi-level metallization
212		CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE-BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR)
213		FIELD EFFECT DEVICE
214		. Charge injection device
215		. Charge transfer device
216		. . Majority signal carrier (e.g., buried or bulk channel, or peristaltic)
217		. . . Having a conductive means in direct contact with channel (e.g., non- insulated gate)
218		. . . High resistivity channel (e.g., accumulation mode) or surface channel (e.g., transfer of signal charge occurs at the surface of the semi-conductor) or minority carriers at input (e.g., surface channel input)
219		. . . Impurity concentration variation
220		. . . . Vertically within channel (e.g., profiled)
221		. . . . Along the length of the channel (e.g., doping variations for transfer directionality)
222		. . . Responsive to non-electrical external signal (e.g., imager)
223		. . . . Having structure to improve output signal (e.g., antiblooming drain)
224		. . . Channel confinement
225		. . Non-electrical input responsive (e.g., light responsive imager, input programmed by size of storage sites for use as a read-only memory, etc.)
226		. . . Sensor element and charge transfer device are of different materials or on different substrates (e.g., "hybrid")
227		. . . With specified dopant (e.g., photoionizable, "extrinsic" detectors for infrared)
228		. . . Light responsive, back illuminated
229		. . . Having structure to improve output signal (e.g., exposure control structure)
230		. . . . With blooming suppression structure
231		. . . 2-dimensional area architecture
232		. . . . Having alternating strips of sensor structures and register structures (e.g., interline imager)
233		. . . . Sensors not overlaid by electrode (e.g., photodiodes)
234		. . . Single strip of sensors (e.g., linear imager)
235		. . Electrical input
236		. . . Signal applied to field effect electrode
237		. . . . Charge-presetting/linear input type (e.g., fill and spill)
238		. . . Input signal responsive to signal charge in charge transfer device (e.g., regeneration or feedback)
239		. . Signal charge detection type (e.g., floating diffusion or floating gate non-destructive output)
240		. . Changing width or direction of channel (e.g., meandering channel)
241		. . Multiple channels (e.g., converging or diverging or parallel channels)
242		. . Vertical charge transfer
243		. . Channel confinement
244		. . Comprising a groove
245		. . Structure for applying electric field into device (e.g., resistive electrode, acoustic traveling wave in channel)
246		. . . Phase structure (e.g., doping variations to provide asymmetry for 2-phase operation; more than four phases or "electrode per bit")
247		. . . . Uniphase or virtual phase structure
248		. . . . 2-phase
249		. . . Electrode structures or materials
250		. . . . Plural gate levels
251		. . Substantially incomplete signal charge transfer (e.g., bucket brigade)
252		. Responsive to non-optical, non-electrical signal
253		. . Chemical (e.g., ISFET, CHEMFET)
254		. . Physical deformation (e.g., strain sensor, acoustic wave detector)
255		. With current flow along specified crystal axis (e.g., axis of maximum carrier mobility)
256		. Junction field effect transistor (unipolar transistor)
257		. . Light responsive or combined with light responsive device
258		. . . In imaging array
259		. . Elongated active region acts as transmission line or distributed active element (e.g., "transmission line" field effect transistor)
260		. . Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell)
261		. . Junction gate region free of direct electrical connection (e.g., floating junction gate memory cell structure)
262		. . Combined with insulated gate field effect transistor (IGFET)
263		. . Vertical controlled current path
264		. . . Enhancement mode or with high resistivity channel (e.g., doping of 1015cm-3 or less)
265		. . . In integrated circuit
266		. . . With multiple parallel current paths (e.g., grid gate)
267		. . . . With Schottky barrier gate
268		. . Enhancement mode
269		. . . With means to adjust barrier height (e.g., doping profile)
270		. . Plural, separately connected, gates control same channel region
271		. . Load element or constant current source (e.g., with source to gate connection)
272		. . Junction field effect transistor in integrated circuit
273		. . . With bipolar device
274		. . . Complementary junction field effect transistors
275		. . . Microwave integrated circuit (e.g., microstrip type)
276		. . . . With contact or heat sink extending through hole in semiconductor substrate, or with electrode suspended over substrate (e.g., air bridge)
277		. . . . With capacitive or inductive elements
278		. . . With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit)
279		. . Pn junction gate in compound semiconductor material (e.g., GaAs)
280		. . With Schottky gate
281		. . . Schottky gate to silicon semiconductor
282		. . . Gate closely aligned to source region
283		. . . . With groove or overhang for alignment
284		. . . Schottky gate in groove
285		. . With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface)
286		. . With non-uniform channel thickness or width
287		. . With multiple channels or chanel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET)
288		. Having insulated electrode (e.g., MOSFET, MOS diode)
289		. . Significant semiconductor chemical compound in bulk crystal (e.g., GaAs)
290		. . Light responsive or combined with light responsive device
291		. . . Imaging array
292		. . . . Photodiodes accessed by FETs
293		. . . . Photoresistors accessed by FETs, or photodetectors separate from FET chip
294		. . . . With shield, filter, or lens
295		. . With ferroelectric material layer
296		. . Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)
297		. . . With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)
298		. . . Capacitor for signal storage in combination with non-volatile storage means
299		. . . Structure configured for voltage converter (e.g., charge pump, substrate bias generator)
300		. . . Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., nondestructive readout dynamic memory cell structure)
301		. . . Capacitor in trench
302		. . . . Vertical transistor
303		. . . . Stacked capacitor
304		. . . . Storage node isolated by dielectric from semiconductor substrate
305		. . . . With means to insulate adjacent storage nodes (e.g., channel stops or field oxide)
306		. . . Stacked capacitor
307		. . . . Parallel interleaved capacitor electrode pairs (e.g., interdigitized)
308		. . . . . With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post)
309		. . . . With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes)
310		. . . With high dielectric constant insulator (e.g., Ta2Os)
311		. . . Storage node isolated by dielectric from semiconductor substrate
312		. . . Voltage variable capacitor (i.e., capacitance varies with applied voltage)
313		. . . Inversion layer capacitor
314		. . Variable threshold (e.g., floating gate memory device)
315		. . . With floating gate electrode
316		. . . . With additional contacted control electrode
317		. . . . . With irregularities on electrode to facilitate charging or discharging of floating electrode
318		. . . . . Additional control electrode is doped region in semiconductor substrate
319		. . . . . Plural additional contacted control electrodes
320		. . . . . . Separate control electrodes for charging and for discharging floating electrode
321		. . . . . With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling
322		. . . . . With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)
323		. . . . With means to facilitate light erasure
324		. . . Multiple insulator layers (e.g., MNOS structure)
325		. . . . Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions)
326		. . . . With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure)
327		. . Short channel insulated gate field effect transistor
328		. . . Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode)
329		. . . Gate controls vertical charge flow portion of channel (e.g., VMOS device)
330		. . . . Gate electrode in groove
331		. . . . . Plural gate electrodes or grid shaped gate electrode
332		. . . . . Gate electrode self-aligned with groove
333		. . . . . With thick insulator to reduce gate capacitance in non-channel areas (e.g., thick oxide over source or drain region)
334		. . . . . In integrated circuit structure
335		. . . Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)
336		. . . . With lightly doped portion of drain region adjacent channel (e.g., LDD structure)
337		. . . . In integrated circuit structure
338		. . . . . With complementary field effect transistor
339		. . . . With means to increase breakdown voltage
340		. . . . With means (other than self-alignment of the gate electrode) to decrease gate capacitance (e.g., shield electrode)
341		. . . . Plural sections connected in parallel (e.g., power MOSFET)
342		. . . . . With means to reduce ON resistance
343		. . . . All contacts on same surface (e.g., lateral structure)
344		. . . With lightly doped portion of drain region adjacent channel (e.g., LDD structure)
345		. . . With means to prevent sub-surface currents, or with non-uniform channel doping
346		. . . Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate)
347		. . Single crystal semiconductor layer on insulating substrate (SOI)
348		. . . Depletion mode field effect transistor
349		. . . With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate
350		. . . Insulated electrode device is combined with diverse type device (e.g., complementary MOSFETs, FET with resistor, etc.)
351		. . . . Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components)
352		. . . Substrate is single crystal insulator (e.g., sapphire or spinel)
353		. . . . Single crystal islands or semiconductor layer containing only one active device
354		. . . . . Including means to eliminate island edge effects (e.g., insulating filling between islands, or channel stop regions in island edges)
355		. . With overvoltage protective means
356		. . . For protecting against gate insulator breakdown
357		. . . . In complementary field effect transistor integrated circuit
358		. . . . . Including resistor element
359		. . . . . . As thin film structure (e.g., polysilicon resistor)
360		. . . . Protection device includes insulated gate transistor structure (e.g., combined with resistor element)
361		. . . . . For operation as bipolar or punchthrough element
362		. . . . Punchthrough or bipolar element
363		. . . . Including resistor element
364		. . With resistive gate electrode
365		. . With plural, separately connected, gate electrodes in same device
366		. . . Overlapping gate electrodes
367		. . Insulated gate controlled breakdown of pn junction (e.g., field plate diode)
368		. . Insulated gate field effect transistor in integrated circuit
369		. . . Complementary insulated gate field effect transistors
370		. . . . Combined with bipolar transistor
371		. . . . Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells
372		. . . . With means to prevent latchup or parasitic conduction channels
373		. . . . With pn junction to collect injected minority carriers to prevent parasitic bipolar transistor action
374		. . . . . Dielectric isolation means (e.g., dielectric layer in vertical grooves)
375		. . . . . With means to reduce substrate spreading resistance (e.g., heavily doped substrate)
376		. . . . . With barrier region of reduced minority carrier lifetime (e.g., heavily doped P+ region to reduce electron minority carrier lifetime, or containing deep level impurity or crystal damage), or with region of high threshold voltage (e.g., heavily doped channel stop region)
377		. . . . With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)
378		. . . Combined with bipolar transistor
379		. . . Combined with passive components (e.g., resistors)
380		. . . . Polysilicon resistor
381		. . . . With multiple levels of polycrystalline silicon
382		. . . With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)
383		. . . . Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium)
384		. . . . Including silicide
385		. . . . Multiple polysilicon layers
386		. . . With means to reduce parasitic capacitance
387		. . . . Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)
388		. . . . . Gate electrode consists of refractory or platinum group metal or silicide
389		. . . . With thick insulator over source or drain region
390		. . . Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))
391		. . . . Selected groups of complete field effect devices having different threshold voltages (e.g., different channel dopant concentrations)
392		. . . Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode)
393		. . . Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor
394		. . . With means to prevent parasitic conduction channels
395		. . . . Thick insulator portion
396		. . . . . Recessed into semiconductor surface
397		. . . . . . In vertical-walled groove
398		. . . . . . Combined with heavily doped channel stop portion
399		. . . . . Combined with heavily doped channel stop portion
400		. . . . With heavily doped channel stop portion
401		. . . With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET)
402		. . With permanent threshold adjustment (e.g., depletion mode)
403		. . . With channel conductivity dopant same type as that of source and drain
404		. . . . Non-uniform channel doping
405		. . . With gate insulator containing specified permanent charge
406		. . . . Plural gate insulator layers
407		. . . With gate electrode of controlled workfunction material (e.g., low workfunction gate material)
408		. . Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)
409		. . With means to increase breakdown voltage (e.g., field shield electrode, guard ring, etc.)
410		. . Gate insulator includes material (including air or vacuum) other than SiO2
411		. . . Composite or layered gate insulator (e.g., mixture such as silicon oxynitride)
412		. . Gate electrode of refractory material (e.g., polysilicon or silicide of a refractory or platinum group metal)
413		. . . Polysilicon laminated with silicide
414		RESPONSIVE TO NON-ELECTRICAL SIGNAL (E.G., CHEMICAL, STRESS, LIGHT, OR MAGNETIC FIELD SENSORS)
415		. Physical deformation
416		. . Acoustic wave
417		. . Strain sensors
418		. . . With means to concentrate stress
419		. . . . With thinned central active portion of semiconductor surrounded by thick insensitive portion (e.g., diaphragm type strain gauge)
420		. . Means to reduce sensitivity to physical deformation
421		. Magnetic field
422		. . With magnetic field directing means (e.g., shield, pole piece, etc.)
423		. . Bipolar transistor magnetic field sensor (e.g., lateral bipolar transistor)
424		. . Sensor with region of high carrier recombination (e.g., magnetodiode with carriers deflected to recombination region by magnetic field)
425		. . Magnetic field detector using compound semiconductor material (e.g., GaAs, InSb, etc.)
426		. . Differential output (e.g., with offset ajustment means or with means to reduce temperature sensitivity)
427		. . Magnetic field sensor in integrated circuit (e.g., in bipolar transistor integrated circuit)
428		. Electromagnetic or particle radiation
429		. . Charged or elementary particles
430		. . . With active region having effective impurity concentration less than 1012 atoms/cm3
431		. . Light
432		. . . With optical element
433		. . . With housing or encapsulation
434		. . . . With window means
435		. . . With optical shield or mask means
436		. . . With means for increasing light absorption (e.g., redirection of unabsorbed light)
437		. . . . Antireflection coating
438		. . . Avalanche junction
439		. . . Containing dopant adapted for photoionization
440		. . . With different sensor portions responsive to different wavelengths (e.g., color imager)
441		. . . Narrow band gap semiconductor (<<1 eV) (e.g., PbSnTe)
442		. . . . II-VI compound semiconductor (e.g., HgCdTe)
443		. . . Matrix or array (e.g., single line arrays)
444		. . . . Light sensor elements overlie active switching elements in integrated circuit (e.g., where the sensor elements are deposited on an integrated circuit)
445		. . . . With antiblooming means
446		. . . . With specific isolation means in intgrated circuit
447		. . . . With backside illumination (e.g., having a thinned central area or a non-absorbing substrate)
448		. . . . With particular electrode configuration
449		. . . Schottky barrier (e.g., a transparent Schottky metallic layer or a Schottky barrier containing at least one of indium or tin (e.g., SnO2, indium tin oxide))
450		. . . . With doping profile to adjust barrier height
451		. . . . Responsive to light having lower energy (i.e., longer wavelength) than forbidden band gap energy of semiconductor (e.g., by excitation of carriers from metal into semiconductor)
452		. . . . With edge protection, e.g., doped guard ring or mesa structure
453		. . . . With specified Schottky metallic layer
454		. . . . . Schottky metallic layer is a silicide
455		. . . . . . Silicide of Platinum group metal
456		. . . . . . Silicide of refractory metal
457		. . . . With particular contact geometry (e.g., ring or grid)
458		. . . PIN detector, including combinations with non-light responsive active devices
459		. . . With particular contact geometry (e.g., ring or grid, or bonding pad arrangement)
460		. . . With backside illumination (e.g., with a thinned central area or non-absorbing substrate)
461		. . . Light responsive pn junction
462		. . . . Phototransistor
463		. . . . With particular doping concentration
464		. . . . With particular layer thickness (e.g., layer less than light absorption depth)
465		. . . . Geometric configuration of junction (e.g., fingers)
466		. . . External physical configuration of semiconductor (e.g., mesas, grooves)
467		. Temperature
468		. . Semiconductor device operated at cryogenic temperature
469		. . With means to reduce temperature sensitivity (e.g., reduction of temperature sensitivity of junction breakdown voltage by using a compensating element)
470		. . Pn junction adapted as temperature sensor
471		SCHOTTKY BARRIER
472		. To compound semiconductor
473		. . With specified Schottky metal
474		. As active junction in bipolar transistor (e.g., Schottky collector)
475		. With doping profile to adjust barrier height
476		. In integrated structure
477		. . With bipolar transistor
478		. . . Plural Schottky barriers with different barrier heights
479		. . . Connected across base-collector junction of transistor (e.g., Baker clamp)
480		. In voltage variable capacitance diode
481		. Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts)
482		. . Microwave transit time device (e.g., IMPATT diode)
483		. With means to prevent edge breakdown
484		. . Guard ring
485		. Specified materials
486		. . Layered (e.g., a diffusion barrier material layer or a silicide layer or a precious metal layer)
487		WITH MEANS TO INCREASE BREAKDOWN VOLTAGE THRESHOLD
488		. Field relief electrode
489		. . Resistive
490		. . Combined with floating pn junction guard region
491		. In integrated circuit
492		. . With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices)
493		. With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices)
494		. Reverse-biased pn junction guard region
495		. Floating pn junction guard region
496		. With physical configuration of semiconductor surface to reduce electric field (e.g., reverse bevels, double bevels, stepped mesas, etc.)
497		PUNCHTHROUGH STRUCTURE DEVICE (E.G., PUNCHTHROUGH TRANSISTOR, CAMEL BARRIER DIODE)
498		. Punchthrough region fully depleted at zero external applied bias voltage (e.g., camel barrier or planar doped barrier devices, or so-called "bipolar SIT" devices)
499		INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS
500		. Including high voltage or high power devices isolated from low voltage or low power devices in the same integrated circuit
501		. . Including dielectric isolation means
502		. . High power or high voltage device extends completely through semiconductor substrate (e.g., backside collector contact)
503		. With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit)
504		. Including means for establishing a depletion region throughout a semi- conductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation)
505		. With polycrystalline semiconductor isolation region in direct contact with single crystal active semiconductor material
506		. Including dielectric isolation means
507		. . With single crystal insulating substrate (e.g., sapphire)
508		. . With metallic conductor within isolating dielectric or between semiconductor and isolating dielectric (e.g., metal shield layer or internal connection layer)
509		. . Combined with pn junction isolation (e.g., isoplanar, LOCOS)
510		. . . Dielectric in groove
511		. . . . With complementary (npn and pnp) bipolar transistor structures)
512		. . . . . Complementary devices share common active region (e.g., integrated injection logic, I2L)
513		. . . . Vertical walled groove
514		. . . . . With active junction abutting groove (e.g., "walled emitter")
515		. . . . With active junction abutting groove (e.g., "walled emitter")
516		. . . . With passive component (e.g., resistor, capacitor, etc.)
517		. . . . With bipolar transistor structure
518		. . . . . With polycrystalline connecting region (e.g., polysilicon base contact)
519		. . . . Including heavily doped channel stop region adjacent groove
520		. . . . Conductive filling in dielectric-lined groove (e.g., polysilicon backfill)
521		. . . . Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.)
522		. . Air isolation (e.g., beam lead supported semiconductor islands)
523		. . Isolation by region of intrinsic (undoped) semiconductor material (e.g., including region physically damaged by proton bombardment)
524		. . Full dielectric isolation with polycrystalline semiconductor substrate
525		. . . With complementary (npn and pnp) bipolar transistor structures
526		. . With bipolar transistor structure
527		. . . Sides of isolated semiconductor islands along major crystal planes (e.g., (111), (100) planes, etc.)
528		. Passive components in ICs
529		. . Including programmable passive component (e.g., fuse)
530		. . . Anti-fuse
531		. . Including inductive element
532		. . Including capacitor component
533		. . . Combined with resistor to form RC filter structure
534		. . . With means to increase surface area (e.g., grooves, ridges, etc.)
535		. . . Both terminals of capacitor isolated from substrate
536		. . Including resistive element
537		. . . Using specific resistive material
538		. . . . Polycrystalline silicon (doped or undoped)
539		. . . Combined with bipolar transistor
540		. . . . With compensation for non-linearity (e.g., dynamic isolation pocket bias)
541		. . . . Pinch resistor
542		. . . . Resistor has same doping as emitter or collector of bipolar transistor
543		. . . . Lightly doped junction isolated resistor (e.g., ion implanted resistor)
544		. With pn junction isolation
545		. . With means to control isolation junction capacitance (e.g., lightly doped layer at isolation junction to increase depletion layer width)
546		. . With structural means to protect against excess or reversed polarity voltage
547		. . With structural means to control parasitic transistor action or leakage current
548		. . At least three regions of alternating conductivity types with dopant concentration gradients decreasing from surface of semiconductor (e.g., "triple-diffused" integrated circuit)
549		. . With substrate and lightly doped surface layer of same conductivity type, separated by subsurface heavily doped region of opposite conductivity type (e.g., "collector diffused isolation" integrated circuit)
550		. . With lightly doped surface layer of one conductivity type on substrate of opposite conductivity type, having plural heavily doped portions of the one conductivity type between the layer and substrate, different ones of the heavily doped portions having differing depths or physical extent
551		. . Including voltage reference element (e.g., avalanche diode, so-called "Zener diode" with breakdown voltage greater than 6 volts or with positive temperature coefficient of breakdown voltage)
552		. . With bipolar transistor structure
553		. . . Transistors of same conductivity type (e.g., npn) having different current gain or different operating voltage characteristics
554		. . . With connecting region made of polycrystalline semiconductor material (e.g., polysilicon base contact)
555		. . . Complementary bipolar transistor structures (e.g., integrated injection logic, I2L)
556		. . . . Including lateral bipolar transistor structure
557		. Lateral bipolar transistor structure
558		. . With base region doping concentration step or gradient or with means to increase current gain
559		. . With active region formed along groove or exposed edge in semiconductor
560		. . With multiple collectors or emitters
561		. . . With different emitter to collector spacings or facing areas
562		. . . With auxiliary collector/re-emitter between emitter and output collector (e.g., "current hogging logic" device)
563		. With multiple separately connected emitter, collector, or base regions in same transistor structure
564		. . Multipe base or collector regions
565		BIPOLAR TRANSISTOR STRUCTURE
566		. Plural non-isolated transistor structures in same structure
567		. . Darlington configuration (i.e., emitter to collector current of input transistor supplied to base region of output transistor)
568		. . . More than two Darlington-connected transistors
569		. . . Complementary Darlington-connected transistors
570		. . . With active components in addition to Darlington transistors (e.g., antisaturation diode, bleeder diode connected antiparallel to input transistor base-emitter junction, etc.)
571		. . . Non-planar structure (e.g., mesa emitter, or having a groove to define resistor)
572		. . . With resistance means connected between transistor base regions
573		. . . With housing or contact structure or configuration
574		. . Complementary transistors share common active region (e.g., integrated injection logic I2L)
575		. . . Including lateral bipolar transistor structure
576		. . . . With contacts of refractory material (e.g., polysilicon, silicide of refractory or platinum group metal)
577		. Including additional component in same, non-isolated structure (e.g., transistor with diode, transistor with resistor, etc.)
578		. With enlarged emitter area (e.g., power device)
579		. . With separate emitter areas connected in parallel
580		. . . With current ballasting means (e.g., emitter ballasting resistors or base current ballasting means)
581		. . . . Thin film ballasting means (e.g., polysilicon resistor)
582		. . With current ballasting means (e.g., emitter ballasting resistors or base current ballasting resistors)
583		. . With means to reduce transistor action in selected portions of transistor (e.g., heavy base region doping under central web of emitter to prevent secondary breakdown)
584		. . With housing or contact (i.e., electrode) means
585		. With means to increase inverse gain
586		. With non-planar semiconductor surface (e.g., groove, mesa, bevel, etc.)
587		. With specified electrode means
588		. . Including polycrystalline semiconductor as connection
589		. Avalanche transistor
590		. With means to reduce minority carrier lifetime (e.g., region of deep level dopant or region of crystal damage)
591		. With emitter region having specified doping concentration profile (e.g., high-low concentration step)
592		. With base region having specified doping concentration profile or specified configuration (e.g., inactive base more heavily doped than active base or base region has constant doping concentration portion (e.g., epitaxial base))
593		. With means to increase current gain or operating frequency
594		WITH GROOVE TO DEFINE PLURAL DIODES
595		VOLTAGE VARIABLE CAPACITANCE DEVICE
596		. With specified dopant profile
597		. . Retrograde dopant profile (e.g., dopant concentration decreases with distance from rectifying junction)
598		. With plural junctions whose depletion regions merge to vary voltage dependence
599		. With means to increase active junction area (e.g., grooved or convoluted surface)
600		. With physical configuration to vary voltage dependence (e.g., mesa)
601		. Plural diodes in same non-isolated structure, or device having three or more terminals
602		. With specified housing or contact
603		AVALANCHE DIODE (E.G., SO-CALLED "ZENER" DIODE HAVING BREAKDOWN VOLTAGE GREATER THAN 6 VOLTS)
604		. Microwave transit time device (e.g., IMPATT diode)
605		. With means to limit area of breakdown (e.g., guard ring having higher breakdown voltage)
606		. . Subsurface breakdown
607		WITH SPECIFIED DOPANT (E.G., PLURAL DOPANTS OF SAME CONDUCTIVITY IN SAME REGION)
608		. Switching device based on filling and emptying of deep energy levels
609		. For compound semiconductor (e.g., deep level dopant)
610		. Deep level dopant
611		. . With specified distribution (e.g., laterally localized, with specified concentration distribution or gradient)
612		. . Deep level dopant other than gold or platinum
613		INCLUDING SEMICONDUCTOR MATERIAL OTHER THAN SILICON OR GALLIUM ARSENIDE (GaAs) (E.G., PbxSn1-xTe)
614		. Group II-VI compound (e.g., CdTe, HgxCd1-xTe)
615		. Group III-V compound (e.g., InP)
616		. Containing germanium, Ge
617		INCLUDING REGION CONTAINING CRYSTAL DAMAGE
618		PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.)
619		. With thin active central semiconductor portion surrounded by thicker inactive shoulder (e.g., for mechanical support)
620		. With peripheral feature due to separation of smaller semiconductor chip from larger wafer (e.g., scribe region, or means to prevent edge effects such as leakage current at peripheral chip separation area)
621		. With electrical contact in hole in semiconductor (e.g., lead extends through semiconductor body)
622		. Groove
623		. Mesa structure (e.g., including undercut or stepped mesa configuration or having constant slope taper)
624		. . With low resistance ohmic connection means along exposed mesa edge (e.g., contact or heavily doped region along exposed mesa to reduce "skin effect" losses in microwave diode)
625		. . Semiconductor body including mesa is intimately bonded to thick electrical and/or thermal conductor member of larger lateral extent than semiconductor body (e.g., "plated heat sink" microwave diode)
626		. . Combined with passivating coating
627		. With specified crystal plane or axis
628		. . Major crystal plane or axis other than (100), (110), or (111) (e.g., (731) axis, crystal plane several degrees from (100) toward (011), etc.)
629		WITH MEANS TO CONTROL SURFACE EFFECTS
630		. With inversion-preventing shield electrode
631		. In compound semiconductor material (e.g., GaAs)
632		. Insulating coating
633		. . With thermal expansion compensation (e.g., thermal expansion of glass passivant matched to that of semiconductor)
634		. . Insulating coating of glass composition containing component to adjust melting or softening temperature (e.g., low melting point glass)
635		. . Multiple layers
636		. . . At least one layer of semi-insulating material
637		. . . Three or more insulating layers
638		. . . With discontinuous or varying thickness layer (e.g., layer covers only selected portions of semiconductor)
639		. . . At least one layer of silicon oxynitride
640		. . . At least one layer of silicon nitride
641		. . . . Combined with glass layer
642		. . . At least one layer of organic material
643		. . . . Polyimide or polyamide
644		. . . At least one layer of glass
645		. . . Insulating layer containing specified electrical charge (e.g., net negative electrical charge)
646		. . Coating of semi-insulating material (e.g., amorphous silicon or silicon-rich silicon oxide)
647		. . Insulating layer recessed into semiconductor surface (e.g., LOCOS oxide)
648		. . . Combined with channel stop region in semiconductor
649		. . Insulating layer of silicon nitride or silicon oxynitride
650		. . Insulating layer of glass
651		. . Details of insulating layer electrical charge (e.g., negative insulator layer charge)
652		. Channel stop layer
653		WITH SPECIFIED SHAPE OF PN JUNCTION
654		. Interdigitated pn junction or more heavily doped side of junction is concave
655		WITH SPECIFIED IMPURITY CONCENTRATION GRADIENT
656		. With high resistivity (e.g., "intrinsic") layer between p and n layers (e.g., PIN diode)
657		. Stepped profile
658		PLATE TYPE RECTIFIER ARRAY
659		WITH SHIELDING (E.G., ELECTRICAL OR MAGNETIC SHIELDING, OR FROM ELECTROMAGNETIC RADIATION OR CHARGE PARTICLES)
660		. With means to shield device contained in housing or package from charged particles (e.g., alpha particles) or highly ionizing radiation (i.e., hard X-rays or shorter wavelength)
661		SUPERCONDUCTIVE CONTACT OR LEAD
662		. Transmission line or shielded
663		. On integrated circuit
664		TRANSMISSION LINE LEAD (E.G., STRIPLINE, COAX, ETC.)
665		CONTACTS OR LEADS INCLUDING FUSIBLE LINK MEANS OR NOISE SUPPRESSION MEANS
666		LEAD FRAME
667		. With dam or vent for encapsulant
668		. On insulating carrier other than a printed circuit board
669		. With stress relief
670		. With separate tie bar element or plural tie bars
671		. . Of insulating material
672		. Small lead frame (e.g., "spider" frame) for connecting a large lead frame to a semiconductor chip
673		. With bumps on ends of lead fingers to connect to semiconductor
674		. With means for controlling lead tension
675		. With heat sink means
676		. With structure for mounting semiconductor chip to lead frame (e.g., configuration of die bonding flag, absence of a die bonding flag, recess for LED)
677		. Of specified material other than copper (e.g., Kovar (T.M.))
678		HOUSING OR PACKAGE
679		. Smart (e.g., credit) card package
680		. With window means
681		. . For erasing EPROM
682		. With desiccant, getter, or gas filling
683		. With means to prevent explosion of package
684		. With semiconductor element forming part (e.g., base, of housing)
685		. Multiple housings
686		. . Stacked arrangement
687		. Housing or package filled with solid or liquid electrically insulating material
688		. With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element (e.g., ring)
689		. . Rigid electrode portion
690		. With contact or lead
691		. . Having power distribution means (e.g., bus structure)
692		. . With particular lead geometry
693		. . . External connection to housing
694		. . . . Axial leads
695		. . . . Fanned/radial leads
696		. . . . Bent (e.g., J-shaped) lead
697		. . . . Pin grid type
698		. . With specific electrical feedthrough structure
699		. . . Housing entirely of metal except for feedthrough structure
700		. . Multiple contact layers separated from each other by insulator means and forming part of a package of housing (e.g., plural ceramic layer package)
701		. Insulating material
702		. . Of insulating material other than ceramic
703		. . Composite ceramic, or single ceramic with metal
704		. . Cap or lid
705		. . Of high thermal conductivity ceramic (e.g., BeO)
706		. . With heat sink
707		. . . Directly attached to semiconductor device
708		. Entirely of metal except for feedthrough
709		. . With specified insulator to isolate device from housing
710		. . With specified means (e.g., lip) to seal base to cap
711		. . With raised portion of base for mounting semiconductor chip
712		. With provision for cooling the housing or its contents
713		. . For integrated circuit
714		. . Liquid coolant
715		. . . Boiling (evaporative) liquid
716		. . . Cryogenic liquid coolant
717		. . Isolation of cooling means (e.g., heat sink) by an electrically insulating element (e.g., spacer)
718		. . Heat dissipating element held in place by clamping or spring means
719		. . . Pressed against semiconductor element
720		. . Heat dissipating element has high thermal conductivity insert (e.g., copper slug in aluminum heat sink)
721		. . With gas coolant
722		. . . With fins
723		. For plural devices
724		. . With discrete components
725		. . With electrical isolation means
726		. . . Devices held in place by clamping
727		. Device held in place by clamping
728		. For high frequency (e.g., microwave) device
729		. Portion of housing of specific materials
730		. Outside periphery of package having specified shape or configuration
731		. With housing mount
732		. . Flanged mount
733		. . Stud mount
734		COMBINED WITH ELECTRICAL CONTACT OR LEAD
735		. Beam leads (i.e., leads that extend beyond the ends or sides of a chip component)
736		. . Layered
737		. Bump leads
738		. . Ball shaped
739		. With textured surface
740		. With means to prevent contact from penetrating shallow pn junction (e.g., prevention of aluminum "spiking")
741		. Of specified material other than unalloyed aluminum
742		. . With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal
743		. . . For compound semiconductor contact material
744		. . For compound semiconductor material
745		. . . Contact for III-V material
746		. . Composite material (e.g., fibers or strands embedded in solid matrix)
747		. . With thermal expansion matching of contact or lead material to semiconductor active device
748		. . . Plural layers of specified contact or lead material
749		. . At least portion of which is transparent to ultraviolet, visible or infrared light
750		. . Layered
751		. . . At least one layer forms a diffusion barrier
752		. . . Planarized to top of insulating layer
753		. . . With adhesion promoting means (e.g., layer of material) to promote adhesion of contact to an insulating layer
754		. . . At least one layer of silicide or polycrystalline silicon
755		. . . . Polysilicon laminated with silicide
756		. . . . Multiple polysilicon layers
757		. . . . Silicide of refractory or platinum group metal
758		. . . Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)
759		. . . . Including organic insulating material between metal levels
760		. . . . Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride)
761		. . . At least one layer containing vanadium, hafnium, niobium, zirconium, or tantalum
762		. . . At least one layer containing silver or copper
763		. . . At least one layer of molybdenum, titanium, or tungsten
764		. . . . Alloy containing molybdenum, titanium, or tungsten
765		. . . At least one layer of an alloy containing aluminum
766		. . . At least one layer containing chromium or nickel
767		. . Resistive to electromigration or diffusion of the contact or lead material
768		. . Refractory or platinum group metal or alloy or silicide thereof
769		. . . Platinum group metal or silicide thereof
770		. . . Molybdenum, tungsten, or titanium or their silicides
771		. . Alloy containing aluminum
772		. . Solder composition
773		. Of specified configuration
774		. . Via (interconnection hole) shape
775		. . Varying width or thickness of conductor
776		. . Cross-over arrangement, component or structure
777		. Chip mounted on chip
778		. Flip chip
779		. Solder wettable contact, lead or bond
780		. Ball or nail head type contact, lead or bond
781		. . Layered contact, lead or bond
782		. Die bond
783		. . With adhesive means
784		. Wire contact, lead or bond
785		. By pressure alone
786		. Configuration or pattern of bonds
787		ENCAPSULATED
788		. With specified encapsulant
789		. . With specified filler material
790		. . Plural encapsulating layers
791		. . Including polysiloxane (e.g., silicone resin)
792		. . Including polyimide
793		. . Including epoxide
794		. . Including glass
795		. With specified filler material
796		. With heat sink embedded in encapsulant
797		ALIGNMENT MARKS
798		MISCELLANEOUS
		******************************
		CROSS-REFERENCE ART COLLECTIONS
		******************************
900		MOSFET TYPE GATE SIDEWALL INSULATING SPACER
901		MOSFET SUBSTRATE BIAS
902		FET WITH METAL SOURCE REGION
903		FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL
904		. With passive components (e.g., polysilicon resistors)
905		PLURAL DRAM CELLS SHARE COMMON CONTACT OR COMMON TRENCH
906		DRAM WITH CAPACITOR ELECTRODES USED FOR ACCESSING (E.G., BIT LINE IS CAPACITOR PLATE)
907		FOLDED BIT LINE DRAM CONFIGURATION
908		DRAM CONFIGURATION WITH TRANSISTORS AND CAPACITORS OF PAIRS OF CELLS ALONG A STRAIGHT LINE BETWEEN ADJACENT BIT LINES
909		MACROCELL ARRAYS (E.G., GATE ARRAYS WITH VARIABLE SIZE OR CONFIGURATION OF CELLS)
910		DIODE ARRAYS (E.G., DIODE READ-ONLY MEMORY ARRAY)
911		LIGHT SENSITIVE ARRAY ADAPTED TO BE SCANNED BY ELECTRON BEAM (E.G., VIDICON DEVICE)
912		CHARGE TRANSFER DEVICE USING BOTH ELECTRON AND HOLE SIGNAL CARRIERS
913		WITH MEANS TO ABSORB OR LOCALIZE UNWANTED IMPURITIES OR DEFECTS FROM SEMICONDUCTORS (E.G., HEAVY METAL GETTERING)
914		POLYSILICON CONTAINING OXYGEN, NITROGEN, OR CARBON (E.G., SIPOS)
915		WITH TITANIUM NITRIDE PORTION OR REGION
916		NARROW BAND GAP SEMICONDUCTOR MATERIAL (<< 1eV)
917		PLURAL DOPANTS OF SAME CONDUCTIVITY TYPE IN SAME REGION
918		LIGHT EMITTING REGENERATIVE SWITCHING DEVICE (E.G., LIGHT EMITTING SCR) ARRAYS, CIRCUITRY, ETC.
919		ELEMENTS OF SIMILAR CONSTRUCTION CONNECTED IN SERIES OR PARALLEL TO AVERAGE OUT MANUFACTURING VARIATIONS IN CHARACTERISTICS
920		CONDUCTOR LAYERS ON DIFFERENT LEVELS CONNECTED IN PARALLEL (E.G., TO REDUCE RESISTANCE)
921		RADIATION HARDENED SEMICONDUCTOR DEVICE
922		WITH MEANS TO PREVENT INSPECTION OF OR TAMPERING WITH AN INTEGRATED CIRCUIT (E.G., "SMART CARD" ANTI-TAMPER)
923		WITH MEANS TO OPTIMIZE ELECTRICAL CONDUCTOR CURRENT CARRYING CAPACITY (E.G., PARTICULAR CONDUCTOR ASPECT RATIO)
924		WITH PASSIVE DEVICE (E.G., CAPACITOR), OR BATTERY AS INTEGRAL PART OF HOUSING OR HOUSING ELEMENT (E.G., CAP)
925		BRIDGE RECTIFIER MODULE
926		ELONGATED LEAD EXTENDING AXIALLY THROUGH ANOTHER ELONGATED LEAD
927		DIFFERENT DOPING LEVELS IN DIFFERENT PARTS OF PN JUNCTION TO PRODUCE SHAPED DEPLETION LAYER
928		WITH SHORTED PN OR SCHOTTKY JUNCTION OTHER THAN EMITTER JUNCTION
929		PN JUNCTION ISOLATED INTEGRATED CIRCUIT WITH ISOLATION WALLS HAVING MINIMUM DOPANT CONCENTRATION AT INTERMEDIATE DEPTH IN EPITAXIAL LAYER (E.G., DIFFUSED FROM BOTH SURFACES OF EPITAXIAL LAYER)
930		THERMOELECTRIC (E.G., PELTIER EFFECT) COOLING

Information Products Division -- Contacts

Questions regarding this report should be directed to:

U.S. Patent and Trademark Office
Information Products Division
PK3- Suite 441
Washington, DC 20231

tel: (703) 306-2600
FAX: (703) 306-2737
email: oeip@uspto.gov

---

Last Modified: 6 October 2000