This class provides for process or apparatus for detecting and correcting errors in electrical pulse or pulse coded data.
This class also provides for process or apparatus for detecting and recovering from faults in electrical computers and digital data processing systems, as well as logic level based systems.
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SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, appropriate subclasses for process and apparatus for measuring, testing or sensing of electric properties or measuring, testing or sensing of nonelectric properties by electric means.
341, Coded data Generation or Conversion, appropriate subclasses for process and apparatus utilizing electrical pulse coding techniques without error correcting/detecting functions for the generating or conversion of coded data.
358, Facsimile and Static Presentation Processing, appropriate subclasses for process and apparatus for testing and performance monitoring of facsimile devices.
365, Static Information Storage and Retrieval, subclass 200 and 201, for process and apparatus including the specifics of memory devices which are tested for defects or erroneous information.
370, Multiplex Communications, appropriate subclasses for process and apparatus for measuring and testing part of a multiplex system.
375, Pulse or Digital Communications, subclass 213 and 224 - 228 for process and apparatus for testing pulse or digital communication systems.
379, Telephonic Communications, subclasses 1-33 for process and apparatus for testing of telephone circuits.
455, Telecommunications, appropriate subclasses for process and apparatus for measuring, testing and monitoring of telecommunication systems.
706, Data Processing: Artificial Intelligence, 1 for fuzzy logic, subclasses 15+ for neural networks and subclasses 45+ for knowledge processing systems.
707, Data Processing: Database and File Management, Data Structures, or Document Processing, subclasses 1-206 for database processing.
708, Electrical Computers - Arithmetic Processing and Calculating, appropriate subclasses for process and apparatus for computer arithmetic circuits.
709, Electrical Computers and Digital Processing Systems: Multiple Computer or Process Coordinating, appropriate subclasses for multiple computer or computer process systems.
710, Electrical Computers and Digital Processing Systems: Input/Output, appropriate subclasses for process and apparatus for computer input or output systems.
711, Electrical Computers and Digital Processing Systems: Memory, 133 for entry replacement strategies and page fault recovery, and subclasses 161+ for data archiving.
712, Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing, appropriate subclasses for process and apparatus for computer structure and program execution systems.
713, Electrical Computers and Digital Processing Systems: Support, appropriate subclasses for process and apparatus for computer cases, housing and supports.
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BUS
A conductor used for transferring data, signals or power.
COMPUTER
A machine that inputs data, processes data, stores data, and outputs data.
DATA
Representation of information in a coded manner suitable for communication, interpretation, or processing.
ADDRESS DATA
Data that represent or identify a source or destination.
INSTRUCTION DATA
Data that represent an operation and identify its operands, if any.
STATUS DATA
Data that represent conditions of data, digital data processing systems, computers, peripherals, memory, etc.
USER DATA
Data other than address data, instruction data, or status data.
DATA PROCESSING
See PROCESSING, below.
DIGITAL DATA PROCESSING SYSTEM
An arrangement of processor(s) in combination with either memory or peripherals, or both, performing data processing.
ERROR
Manifestation of a fault as an undesired event that occurs when actual behavior deviates from the behavior that is required by initial specification. This includes a change in information content of pulse or pulse coded data to a state or value other than the normal state or value of a properly operating device or system.
FAULT
A flaw in a functional unit (hardware or software).
INFORMATION
Meaning that a human being assigns to data by means of the conventions applied to that data.
MEMORY
A functional unit to which data can be stored and from which data can be retrieved.
PERIPHERAL
A functional unit that transmits data to or receives data from a computer to which it is coupled.
PROCESSING
Methods or apparatus performing systematic operations upon data or information exemplified by functions such as data or information transferring, merging, sorting, and computing (i.e., arithmetic operations or logical operations).
(1) Note. In this class, the glossary term data is used to modify processing in the term data processing; whereas the term digital data processing system refers to a machine performing data processing.
PROCESSOR
A functional unit that interprets and executes instruction data.
RECOVERY
Responding to a fault in a system by either returning a system to a previous level of correct operation, achieving a degraded level of correct operation, or safely shutting down the system.
SECURITY
Extent of protection for system hardware, software, or data from maliciously caused destruction, unauthorized modification, or unauthorized disclosure.

RELIABILITY AND AVAILABILITY:
This subclass is indented under the class definition. Subject matter including means or steps for increasing a conditional probability of correctly performing services (e.g., data processing) throughout a time interval, given correct performance at the beginning of the interval, or for increasing the probability of correctly performing services at any given instant.
(1) Note. Classification in this array requires more than nominal recitation of data processing components in combination with means or steps for furthering correct data processing operations by mechanisms including error detecting, performance monitoring, fault locating, and fault recovery.
(2) Note. The species of reliability and availability directed to memory accessing and control with data archiving, backups, device access limiting, and security is classified elsewhere. See the SEE OR SEARCH CLASS notes below. Other species of reliability and availability in memory accessing and control such as isolating failed memory and storing redundant data are classified in this array.
(3) Note. Reliability features in a data processing control system are classified elsewhere.

SEE OR SEARCH THIS CLASS, SUBCLASS:
746 for generic data error detection and correction, and fault detection and recovery.

SEE OR SEARCH CLASS:
380, Cryptography, subclass 4 for stored digital data access or copy prevention in combination with data encryption; e.g., software program protection or computer virus detection in combination with data encryption.
700, Data Processing: Generic Control Systems or Specific Applications, subclasses 79-82 for reliability features in a data processing generic control system.

Fault recovery:
This subclass is indented under subclass 1. Subject matter further including means or steps for responding to a failure by either returning a system to a previous level of correct operation, achieving a degraded level of correct operation, or safely shutting down the system after detecting the error or locating the fault.
(1) Note. Classification here requires significant data processing features claimed. For fault recovery in a system without significant data processing method or apparatus, classification is elsewhere. See the SEE OR SEARCH THIS CLASS, SUBCLASS and SEE OR SEARCH CLASS notes below.
(2) Note. Classification here requires notification or detection of the fault, its location, and a further action. Subcombinations used in the process of fault recovery; e.g., fault locating, are classified below.
(3) Note. "Page faults" are a species of faults peculiar to memory accessing and are classified elsewhere in this class. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:
746 for data error detection and correction of general utility.

SEE OR SEARCH CLASS:
711, Electrical Computers and Digital Processing Systems: Memory, 133 for entry replacement strategies and page fault recovery.

By masking or reconfiguration:
This subclass is indented under subclass 2. Subject matter further including means or steps for recovery by selecting a correct output from a concurrently active redundant functional unit in place of the output of the failed functional unit, or by replacing or isolating the failed functional unit.
(1) Note. This subclass is for fault recovery by masking or reconfiguration in combination with significant data processing. Generic fault recovery is classified elsewhere. See the SEE OR SEARCH CLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:
825 for fault recovery by replacing or isolating the failed functional unit not provided for elsewhere.

Of network:
This subclass is indented under subclass 3. Subject matter further including means or steps for recovery at a network level (e.g., recovery from nodal failures).

SEE OR SEARCH CLASS:
340, Communications: Electrical, various subclasses for residual electrical communication systems, subclass 827 for alternate routing in a plural stage communication system, and see related Class 342 and Class 343.
342, Communications: Directive Radio Wave Systems and Devices (e.g., Radar, Radio Navigation), various subclasses for alternate routing in a plural stage radar network.
343, Communications: Radio Wave Antennas, various subclasses for alternate routing in a plural antenna system.
370, Multiplex Communications, 216 for fault recovery and subclasses 229+ for data flow congestion prevention and control in a multiplex communication system.
375, Pulse or Digital Communications, various subclasses for generic pulse or digital communication systems.

Of memory or peripheral subsystem:
This subclass is indented under subclass 3. Subject matter further including means or steps for recovery from a fault of a memory function level or the peripheral function level, or for recovery limited to a specialized processor accessing either memory, peripheral, or other I/O device.
(1) Note. "Page faults" are a species of faults peculiar to memory accessing and are classified elsewhere. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:
710 for memory fault recovery of general utility without significant data processing features claimed.

SEE OR SEARCH CLASS:
710, Electrical Computers and Digital Processing Systems-Input/Output:, 1, for transferring data from one or more peripherals to one or more computers for the latter to process, store, or further transfer or for transferring data from the computers to the peripherals (i.e., Input/Output data processing).
711, Electrical Computers and Digital Processing Systems: Memory, 100 for means (e.g., processor, controller, etc.) or steps for governing memory in a digital data processing system or the passage (e.g., reading or writing) of data thereto and subclasses 133+for entry replacement strategies and page fault recovery.

Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data):
This subclass is indented under subclass 5. Subject matter further including means or steps for recovery by accessing redundant stored data.
(1) Note. This and indented subclasses rely on information which is a function of the actual data of concern as exemplified in one simple form by parity data. The species of fault recovery or avoidance concerned with storing archival verbatim copies of data is classified elsewhere. See SEE OR SEARCH CLASS notes below.
(2) Note. Parity and error-correction coded storage of general utility in a system without data processing features claimed are classified elsewhere in this class. See SEE OR SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:
763 for memory access block coding.
805 for storage accessing error/fault detection techniques.

SEE OR SEARCH CLASS:
711, Electrical Computers and Digital Processing Systems: Memory, 161 for preventing the corruption, loss, alteration, or disclosure of data by storing, as in making backup copies.

Reconfiguration (e.g., adding a replacement storage component):
This subclass is indented under subclass 6. Subject matter further including means or steps for statically replacing a failed memory component.
(1) Note. Classification here requires more than selecting a correct output from a concurrently active redundant functional unit in place of the output of the failed component.

SEE OR SEARCH THIS CLASS, SUBCLASS:
710 for recovery from failure of memory, by replacing or isolating the failed memory, in a system without significant data processing features claimed.

Isolating failed storage location (e.g., sector remapping):
This subclass is indented under subclass 5. Subject matter further including means or steps for recovery by disabling access to a failed memory location.
(1) Note. Classification here requires more than selecting a correct output from a concurrently active redundant functional unit in place of the output of the failed component.

SEE OR SEARCH THIS CLASS, SUBCLASS:
710 for recovery from failure of memory, by replacing or isolating the failed memory, in a system without significant data processing features.

SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass 200
and 201 for bad bit and testing of static storage.
711, Electrical Computers and Digital Processing Systems: Memory, 170 for automatically determined memory space allocation.

Access processor affected (e.g., I/O processor, MMU, DMA processor):
This subclass is indented under subclass 5. Subject matter further including means or steps for recovery from fault of an access processor (e.g., memory management unit (MMU), direct memory access (DMA) processor, I/O processor, etc.).

SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems - Processing Architecture or Instruction Processing (e.g., Processors), appropriate subclasses for digital data processing system architecture, per se.

Of processor:
This subclass is indented under subclass 3. Subject matter further including means or steps for recovery from fault of a processor.

SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems-Processing Architecture or Instruction Processing (e.g., Processors), appropriate subclasses for digital data processing system architecture, per se.

Concurrent, redundantly operating processors:
This subclass is indented under subclass 10. Subject matter further including means or steps for recovery employing redundant processors substantially simultaneously performing the same operation.

SEE OR SEARCH CLASS:
700, Data Processing: Generic Control Systems or Specific Applications, subclass 3 for master/slave processors in a
data processing generic control system, and subclasses 79-82 for protection or reliability in a digital data processing control system.

Synchronization maintenance of processors:
This subclass is indented under subclass 11. Subject matter further including means or steps for maintaining processor state synchronization to achieve redundancy of operation.
(1) Note. Classification here requires a redundant processor for the purpose of reliability, such as by consideration of state of internal registers and the like of the redundant processors and thus the machines themselves. Synchronization in the form of timing and clock skew is classified elsewhere. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below.
(2) Note. Classification here requires the existence of a fault condition. Synchronization maintenance at the clock level, however, is classified elsewhere. See the search class notes below.

SEE OR SEARCH CLASS:
375, Pulse or Digital Communications, 354 for communications synchronizing.
709, Electrical Computers and Digital Processing Systems-Multiple Computer or Process Coordinating, appropriate subclasses for multicomputer and synchronizing, and for synchronization maintenance of plural processors, per se.
712, Electrical Computers and Digital Processing Systems-Processing Architecture or Instruction Processing (e.g., Processors), appropriate subclasses for task management, per se.
713, Electrical Computers and Digital processing Systems-Support, 400, for clock synchronization, per se, subclasses 500+, for digital data processing system clock, pulse and timing interval generation, per se.

Prepared backup processor (e.g., initializing cold backup) or updating backup processor (e.g., by checkpoint message):
This subclass is indented under subclass 10. Subject matter further including means or steps for readying a backup
processor or digital data processing system to replace a failed primary processor or digital data processing system, or to receive recent processing result(s) from a backup processor or digital data processing system that may be relied upon.
(1) Note. Classification here allows for the backup processor or digital data processing system to be performing operations unrelated to backup operation before or after failure of the primary processor or digital data processing systems.

SEE OR SEARCH CLASS:
700, Data Processing: Generic Control Systems or Specific Applications, subclasses 2-7 for data processing control system applications employing plural processors, and subclasses 79-82 for protection or reliability in a digital data processing system based control system.

Of power supply:
This subclass is indented under subclass 3. Subject matter further including means or steps for recovery using power supply subsystem component redundancy.

SEE OR SEARCH CLASS:
713, Electrical Computers and Digital Processing Systems-Support, 300, for power control in a digital data processing system environment, and subclass 321 for electrical digital calculating computer (i.e., calculator) with power saving feature.

State recovery (i.e., process or data file):
This subclass is indented under subclass 2. Subject matter further including means or steps for recovery by restoring data in a data file, or data for a process, to data at a previous point in time.
(1) Note. The species of fault recovery or avoidance concerned with storing verbatim copies of data is classified elsewhere. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below.
(2) Note. Parity and error-correction coded storage of general utility in a system without data processing features
claimed is classified elsewhere.
(3) Note. This state recovery subclass provides for reliability and availability recovery under the condition of a fault. Data management, per se, is classified elsewhere. See the search class notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:
6 for recovery by accessing redundant stored data.
763 for memory access block coding.
805 for storage accessing error/fault detection techniques.

SEE OR SEARCH CLASS:
711, Electrical Computers and Digital Processing Systems: Memory, 141 for cache memory coherency, per se; subclasses 147+ for shared memory data processing which may employ data management principles; and subclasses 161+ for preventing the corruption, loss, alteration, or disclosure of data by storing, as in making backup copies.
712, Electrical Computers and Digital Processing Systems-Processing Architecture or Instruction processing (e.g., processors), appropriate subclasses for source code management and software version management.

Forward recovery (e.g., redoing committed action):
This subclass is indented under subclass 15. Subject matter further including means or steps for recovery by re-executing an operation in response to detecting an error in an operation.
(1) Note. Recovery by operation retry or error detection by sequential repetition in a system without data processing features is classified elsewhere.

SEE OR SEARCH THIS CLASS, SUBCLASS:
822 for sequential repetition.

SEE OR SEARCH CLASS:
707, Data processing-Database and File Management, Data Structures, or Document Processing, subclass 202 for database file recovery.

Reexecuting single instruction or bus cycle:
This subclass is indented under subclass 16. Subject matter further including means or steps for recovery by retrying single instruction or bus cycle.

SEE OR SEARCH CLASS:
710, Electrical Computers and Digital processing Systems-Input/Output, 100, for system intraconnecting and bus processing, per se.

Transmission data record (e.g., for retransmission):
This subclass is indented under subclass 15. Subject matter further including means or steps for recovery of a communication process (e.g., a session) using a record.

SEE OR SEARCH THIS CLASS, SUBCLASS:
748 for retransmission in a system without data processing features claimed.

SEE OR SEARCH CLASS:
710, Electrical Computers and Digital processing Systems-Input/Output, appropriate subclasses for I/O processing and communication between computers and peripherals.

Undo record:
This subclass is indented under subclass 15. Subject matter further including means or steps for recovery of data in the presence of uncommitted action using a record of the data created before the action.

SEE OR SEARCH CLASS:
707, Data processing-Database and File Management, Document Processing, 200, for database and file maintenance in the absence of a fault condition, subclasses 500+ for a word data processing applications on computers and subclasses 530+, for editing in a text data processing applications.

Plural recovery data sets containing set interrelation data (e.g., time values or log record numbers):
This subclass is indented under subclass 15. Subject matter further including means or steps for recovery using sets of sequenced or linked recovery data containing set sequencing or linking data.

State validity check:
This subclass is indented under subclass 15. Subject matter further including means or steps wherein recovery is controlled by verifying the accuracy of the state data.

With power supply status monitoring:
This subclass is indented under subclass 15. Subject matter further including means or steps wherein recovery is controlled by a power supply status monitor.

SEE OR SEARCH CLASS:
713, Electrical Computers and Digital Processing Systems-Support, subclass 321 for electrical digital calculating computer (i.e., calculator) with power saving feature, and subclass 340, for generic power control monitoring in a digital data processing system environment.

Resetting processor:
This subclass is indented under subclass 2. Subject matter further including means or steps for recovery using clearing or initializing of a processor register.

Safe shutdown:
This subclass is indented under subclass 2. Subject matter further including means or steps for recovery including termination of a system component to a safe condition.
(1) Note. Isolating (i.e., disabling) an output of a failed network, processor, memory, peripheral, I/O, or power supply component is classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:
4 for network affected fault recovery.
5 for memory or peripheral subsystem affected.
8 for isolating failed storage locations.
10 for processor affected fault recovery.
14 for power supply affected fault recovery.

SEE OR SEARCH CLASS:
713, Electrical Computers and Digital Processing Systems-Support, 300, for power control in a digital data processing system environment.

Fault locating (i.e., diagnosis or testing):
This subclass is indented under subclass 1. Subject matter further including means or steps for pinpointing a fault using either a reactive diagnosing or a proactive testing, including testing for developmental stage fault avoidance, for assurance, or for maintenance.
(1) Note. An invention directed to locating a fault in a digital data processing system including more than nominal data processing, or where the fault is specific to a nongeneral use of a digital data processing system, is classified here. fault locating in combination with a specific art device not of the basic subject matter of this class is classified with the art device.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, subclass 73.1 for various electrical testing arrangements that may include fault locating.
370, Multiplex Communications, 241 for diagnostic testing in multiplex communications.
399, Electrophotography, 9 for diagnostic testing of a photocopier, including computer controlled malfunction warning and recovery.

Artificial intelligence (e.g., diagnostic expert system):
This subclass is indented under subclass 25. Subject matter wherein the testing is performed using an artificial intelligence technique; e.g., fault tree, reasoning rules, self-learning.

SEE OR SEARCH CLASS:
706, Data Processing: Artificial Intelligence, appropriate subclasses, for artificial intelligence, per se.

Particular access structure:
This subclass is indented under subclass 25. Subject matter further including means or steps related to an access structure specialized for observing or controlling a test or diagnosis.

Substituted emulative component (e.g., emulator microprocessor):
This subclass is indented under subclass 27. Subject matter further including means or steps for using a tester component that can emulate (i.e., functionally operate as) a normal component in the tested system.

SEE OR SEARCH CLASS:
395, Information Processing System Organization, subclass 500, for compatibility, simulation, and emulation of system components.

Memory emulator feature:
This subclass is indented under subclass 28. Subject matter further including means or steps for using memory that can functionally replace a system component.
(1) Note. For classification here the replaced component need not be a memory.

SEE OR SEARCH CLASS:
703, Data Processing: Structural Design, Modeling, Simulation, and Emulation, appropriate subclasses for general purpose simulation or emulation of system components.

Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path):
This subclass is indented under subclass 27. Subject matter further including means or steps for testing or diagnostic access using specialized testing or diagnosing hardware permanently built into a component of the system being tested or diagnosed.

Additional processor for in-system fault locating (e.g., distributed diagnosis program):
This subclass is indented under subclass 27. Subject matter further including an additional processor for controlling all or part of in-system testing or diagnosis.

Particular stimulus creation:
This subclass is indented under subclass 25. Subject matter further including means or steps for selection or generation of a signal (i.e., data) for testing or diagnosing.

SEE OR SEARCH THIS CLASS, SUBCLASS:
712 for memory testing including pattern generation.

SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass 201 for static memory testing.

Derived from analysis (e.g., of a specification or by simulation):
This subclass is indented under subclass 32. Subject matter further including means or steps for deriving a test or diagnosis program based on an analysis of specification, design, or output of the system to be tested or diagnosed.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, subclass 73.1 for various electrical testing arrangements that may include fault locating.
703, Data Processing: Structural Design, Modeling, Simulation, and Emulation, subclasses 13-22 for simulating electronic device and electrical system.
716, Data Processing: Design and Analysis of Circuit or Semiconductor Mask, appropriate subclasses for designing and analyzing circuit or semiconductor mask.

Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping):
This subclass is indented under subclass 32. Subject matter further including means or steps for controlling a processor or digital data processing system to be tested or diagnosed by applying an interrupt, halt, or clock signal to a processor or digital data processing system.

SEE OR SEARCH CLASS:
395, Information Processing System Organization, 701, for software development tools,
710, Electrical Computers and Digital Processing Systems-Input/Output, 48, for Input/Output device interrupt processing.
711, Electrical Computers and Digital Processing Systems: Memory, subclass 204 for virtual address branch or jump address predicting; and subclasses 213 for generalized prefetch, look-ahead, jump, or predictive address generating.
712, Electrical Computers and Digital Processing Systems Processing Architecture and Instruction Processing (e.g., Processors), subclass 227, for instruction processing in support of testing, debugging, emulation, etc.
713, Electrical Computers and Digital Processing Systems-Support, 500, for clock processing, per se.

Substituted or added instruction (e.g., code instrumenting, breakpoint instruction):
This subclass is indented under subclass 32. Subject matter further including means or steps for substituting or adding a testing or diagnosing instruction into a program or instruction data stream of a processor or digital data processing system being tested or diagnosed.

SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems-Processing Architecture and Instruction Processing (e.g., Processors), appropriate subclasses for instruction processing, per se, including instruction alignment, fetching and decoding, and for processing control at the processor level, per se, particularly subclass 227, for instruction processing in support of testing, debugging, emulation, etc.

Test sequence at power-up or initialization:
This subclass is indented under subclass 32. Subject matter further including means or steps for performing a sequence of tests automatically in response to a power-up or initialization action.

SEE OR SEARCH CLASS:
710, Electrical Computers and Digital Processing Systems-Input/Output, appropriate subclasses, for assigning operating characteristics to peripherals, particularly subclass 104, for utilizing a hardware structure for providing a processor with an arrangement of the digital data processing system including characteristics of the digital data processing system's components.
711, Electrical Computers and Digital Processing Systems: Memory, subclass 170 for automatically determining and allocating memory space or specifying an allocation.
713, Electrical Computers and Digital Processing Systems-Support, subclasses 1-100, for digital data processing system initialization and configuration at boot-time.

Analysis (e.g., of output, state, or design):
This subclass is indented under subclass 25. Subject matter further including means or steps for evaluating the output, state, or design, of a computer system or a processor or a program, for fault locating.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, subclass 73.1 for various electrical testing arrangements that may include fault locating.
395, Information Processing System Organization, 500.02 for circuit design and subclasses 500.34+ for simulating electronic device and electrical system.

Of computer software:
This subclass is indented under subclass 37. Subject matter further including means or steps for locating a fault in software or testing software.
(1) Note. This subclass also provides for detecting an error in instruction data in combination with a digital data processing system. Generic coded information error detection is classified elsewhere. See SEARCH CLASS notes below.
(2) Note. This subclass also provides for fault locating in software analysis by mechanisms such as debugging, automatic code generating, object oriented design, etc.

SEE OR SEARCH THIS CLASS, SUBCLASS:
799 for coded information error detecting.

Monitor recognizes sequence of events (e.g., protocol or logic state analyzer):
This subclass is indented under subclass 37. Subject matter further including means or steps for locating a fault by using a monitor for classifying or otherwise recognizing a sequence of events.

SEE OR SEARCH CLASS:
709, Electrical Computers and Digital Processing Systems-Multiple Computer or Process Coordinating, subclass 224 for computer network managing including monitoring.

Component dependent technique:
This subclass is indented under subclass 25. Subject matter further including means or steps for fault locating that are specific to a device under test.

For reliability enhancing component (e.g., testing backup spare, or fault injection):
This subclass is indented under subclass 40. Subject matter further including means or steps for fault locating specific to fault in a reliability enhancing component.

Memory or storage device component fault:
This subclass is indented under subclass 40. Subject matter further including means or steps for fault locating specific to a fault in a memory.

Bus, I/O channel, or network path component fault:
This subclass is indented under subclass 40. Subject matter further including means or steps for fault locating specific to a fault in a bus, peripheral or I/O channel, or network path.

SEE OR SEARCH CLASS:
710, Electrical Computers and Digital Processing Systems-Input/Output, 100, for subject matter directed to system intraconnecting and bus access processing.

Peripheral device component fault:
This subclass is indented under subclass 40. Subject matter further including means or steps for fault locating specific to a fault in a peripheral device.

SEE OR SEARCH CLASS:
710, Electrical Computers and Digital Processing Systems-Input/Output, appropriate subclasses, for subject matter directed to Input/Output processing and communication between peripherals and computers or digital data processing systems.

Output recording (e.g., signature or trace):
This subclass is indented under subclass 25. Subject matter further including means or steps for recording output from the system under test or diagnosis.

SEE OR SEARCH THIS CLASS, SUBCLASS:
47 for error logging without recording.
48 for error detecting, per se.

Operator interface for diagnosing or testing:
This subclass is indented under subclass 25. Subject matter further including means or steps for interfacing with an operator for fault locating.

SEE OR SEARCH CLASS:
345, Computer Graphics Processing, Operator Interface Processing, and Selective Visual Display Systems, appropriate subclasses for information displaying and particularly 326 for computer graphics operator interface.

Performance monitoring for fault avoidance:
This subclass is indented under subclass 1. Subject matter further including means or steps for monitoring event duration and event counts for anticipating or recognizing faults.
(1) Note. This subclass relates to the fault avoidance species of reliability.
(2) Note. This subclass includes event duration and counting arrangements for statistical analysis of system operations
and predictive methods of fault avoidance.

SEE OR SEARCH CLASS:
368, Horology: Time Measuring Systems or Devices, appropriate subclasses for time measurement.
377, Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems, 64 for shift registers, and subclasses 107+ and 11+ for counters.
702, Data Processing-Measuring and Testing, appropriate subclasses for measuring, monitoring, and testing applications of computers.
705, Data Processing - Financial. Business Practice, Management, or Cost/Price Determination, 7 for operations research.
708, Electrical Computers-Arithmetic Processing and Calculating, 200 for various arithmetic data processing operations performed by digital calculating computers.
709, Electrical Computers and Digital Processing Systems-Multiple Computer or Process Coordination, subclass 224, for computer network managing including monitoring.

Error detection or notification:
This subclass is indented under subclass 1. Subject matter further including means or steps for automated on-line sensing of errors, or for storing or propagating such error information (e.g., error logging).

SEE OR SEARCH THIS CLASS, SUBCLASS:
1 for fault recovery in combination with error detecting or notifying.
25 for fault locating combined with error detecting or notifying.
47 for performance monitoring for fault avoidance in combination with error detecting or notifying.

State error (i.e., content of instruction, data, or message):
This subclass is indented under subclass 48. Subject matter
further including means or steps for detecting an error based on the information content of an instruction, a message, or data.

State out of sequence:
This subclass is indented under subclass 49. Subject matter wherein an ordering of state information related to a succession of data, instructions etc., is the basis for state analysis.

SEE OR SEARCH CLASS:
710, Electrical Computers and Digital Processing Systems-Input/Output, 260 for Input/Output device interrupt processing.
711, Electrical Computers and Digital Processing Systems: Memory, subclass 204 for virtual address branch or jump address predicting; and subclass 213 for generalized prefetch, look-ahead, jump, or predictive address generating.
712, Electrical Computers and Digital Processing Systems-Processing Architecture and Instruction Processing (e.g., Processors), appropriate subclasses for instruction fetching and prefetching and for branching instruction processing and for task management and control, per se.

Control flow state sequence monitored (e.g., watchdog processor for control-flow checking):
This subclass is indented under subclass 50. Subject matter to detect state errors in an instruction data sequence.

Error checking code:
This subclass is indented under subclass 50. Subject matter for detecting consistency of information by using a code (e.g., parity, etc.) which is generated from the information.
(1) Note. Error checking codes are a function of the actual data of concern, as exemplified in one simple form by parity data.

SEE OR SEARCH THIS CLASS, SUBCLASS:
763 for memory access block coding, and subclass 805 for storage accessing.

SEE OR SEARCH CLASS:
711, Electrical Computers and Digital Processing Systems: Memory, 161 for preventing the corruption, loss, alteration, or disclosure of data by storing, as in making backup copies.

Address error:
This subclass is indented under subclass 49. Subject matter further including means or steps for detection or notification of error of address state.

Storage content error:
This subclass is indented under subclass 49. Subject matter further including means or steps for detection or notification of error of storage state.

SEE OR SEARCH CLASS:
711, Electrical Computers and Digital Processing Systems: Memory, subclass 144 for cache status data bits (e.g., bits indicating modified, valid, dirty data), wherein coherency for each unit or block of data includes associated identifier bit(s) to indicate the validity status of an associated cached location; subclass 156 for status storage control techniques including provisions for storing status data (e.g., control status words, program status words, etc.) associated with memory accessing and control; and subclass 165 for movement/transfers of data amongst locations within a same memory level.

Timing error (e.g., watchdog timer time-out):
This subclass is indented under subclass 48. Subject matter further including means or steps for detection or notification of error of timing.

SEE OR SEARCH CLASS:
709, Electrical Computers and Digital Processing Systems-Multiple Computer or Process Coordinating, 1 for task management, per se, and subclass 400 for synchronization maintenance of plural processors, per se.
713, Electrical Computers and Digital Processing Systems-Support, 400, for clock synchronization, per se, and subclasses 500+, for digital data processing system clock, pulse and timing interval generation, per se.

Bus or I/O channel device fault:
This subclass is indented under subclass 55. Subject matter further including means or steps for detecting errors related to a flaw in a bus, peripheral, or I/O channel device.

SEE OR SEARCH CLASS:
710, Electrical Computers and Digital Processing Systems: Input/Output, appropriate subclasses for system intraconnecting and bus processing, per se.

Error forwarding and presentation (e.g., operator console, error display):
This subclass is indented under subclass 48. Subject matter further including means or steps for propagating error information so as to make notification of detected error.

SEE OR SEARCH CLASS:
345, Computer Graphics processing, Operator Interface processing, and Selective Visual Display Systems, appropriate subclasses for information displaying.

SKEW DETECTION/CORRECTION:
This subclass is indented under the class definition. Subject matter in which an error caused by the time delay between plural parallel bits forming a byte or data word is detected or corrected.

SEE OR SEARCH CLASS:
360, Dynamic Magnetic Information Storage or Retrieval, subclass 26 for electronically correcting phasing errors between related information signals.

DATA FORMATTING TO IMPROVE ERROR DETECTION/CORRECTION CAPABILITY:
This subclass is indented under the class definition. Subject matter in which a change in data format or sequence is utilized to improve the error detection/correction capability of a coding scheme.

Memory access (e.g., address permutation):
This subclass is indented under subclass 701. Subject matter which changes the format of digital data by having the signal with the data written into or read out of a storage device.
(1) Note. Address permutation arrangements are included in this subclass.

SEE OR SEARCH THIS CLASS, SUBCLASS:
718 for diagnostic testing of a memory.

TESTING OF ERROR-CHECK SYSTEM:
This subclass is indented under the class definition. lSubject matter in which the proper operation of the error detection/correction or fault detection/recovery apparatus itself is verified.

Error count or rate:
This subclass is indented under the class definition. Subject matter which determines the number of bits in error or the number of bits in error per unit of time.

SEE OR SEARCH THIS CLASS, SUBCLASS:
798 for this subject matter combined with control of synchronization in response to an error detection signal.

Pseudo-Error rate:
This subclass is indented under subclass 704. Subject matter having a main data path and a secondary data path having intentionally degraded performance connected in parallel, the secondary path having a decision device to compare and evaluate the disagreement between the paths.
(1) Note. Each disagreement is called a pseudo-error.

Up-down counter:
This subclass is indented under subclass 704. Subject matter including an reversible accumulating register which counts up in response to an error and counts down in response to an error-free increment of time.

SEE OR SEARCH CLASS:
377, Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems, appropriate subclasses for up-down counters per se.

Synchronization control:
This subclass is indented under subclass 704. Subject matter in which a determination of the error rate is used to control synchronization between devices.

SEE OR SEARCH THIS CLASS, SUBCLASS:
798 for error detection controlled synchronization control other than by error rate.

Shutdown or establishing system parameter (e.g., transmission rate):
This subclass is indented under subclass 704. Subject matter
including control of system operation by either deactivation of the system, or controls a parameter related to normal system operation, in response to error count or error rate.

DATA PULSE EVALUATION/BIT DECISION:
This subclass is indented under the class definition. Subject matter in which the information bearing parameter (amplitude, pulse position, etc.) of a data pulse is evaluated to determine the proper logic state or value.
(1) Note. Subject matter in this subclass relates to determining if a data pulse represents a particular given logic state, e.g., logic one as opposed to logic zero.

SEE OR SEARCH CLASS:
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, 1 for pulse selecting means.
329, Demodulators, 311 for pulse demodulation or detection, per se.

REPLACEMENT OF MEMORY SPARE LOCATION, PORTION, OR SEGMENT:
This subclass is indented under the class definition. Subject matter in which the spare apparatus comprises only a location, or a contiguous group of locations of memory.

SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass 200 and 201 for bad bit and testing read/write circuits, respectively.

Spare row or column:
This subclass is indented under subclass 710. Subject matter spare apparatus comprises only a column or row within a memory device or element.

TRANSMISSION FACILITY TESTING:
This subclass is indented under the class definition. Subject matter in which the diagnostic testing is performed upon a channel of a transmission medium with a device for supplying digital data thereto.
(1) Note. The transmission facility includes the transmission medium and all associated equipment required to transmit a message.

SEE OR SEARCH CLASS:
370, Multiplex Communications, 241 for testing of multiplex communication systems.
375, Pulse or Digital Communications, 224 for testing of pulse or digital communications system.
379, Telephonic Communications, 1 for diagnostic testing of telephone equipment.

For channel having repeater:
This subclass is indented under subclass 712. Subject matter wherein a transmission channel has a repeating amplifier.

By tone signal:
This subclass is indented under subclass 712. Subject matter which includes application of a test signal composed of one or more tone signals.

Test pattern with comparison:
This subclass is indented under subclass 712. Subject matter in which the transmission facility is tested by applying a test pattern to the device under test and comparing the output to a reference test pattern.

Loop-back:
This subclass is indented under subclass 715. Subject matter in which the transmission facility is configured so that the receiver shunts the test pattern back to transmitter for comparison at the transmitter.

Loop or ring configuration:
This subclass is indented under subclass 712. Subject matter in which a plurality of transmission stations or devices are configured in a serial fashion to form a loop or ring.

MEMORY TESTING:
This subclass is indented under the class definition. Subject matter in which the diagnostic testing is performed upon an information signal storage device.

SEE OR SEARCH THIS CLASS, SUBCLASS:
710 for fault recovery of memory devices.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, 210 for testing of magnetic memory elements, per se.
360, Dynamic Magnetic Information Storage or Retrieval, subclass 26, 47, and 53 for testing of dynamic magnetic memory systems.
365, Static Information Storage and Retrieval, subclass 200 a bad bit memory used to store information; and subclass 201 for specifics of a memory which is tested but doesn't include data processing techniques.
386, Television Signal Processing for Dynamic Recording or Reproducing, 2 and 47+ for drop-out detection or correction, subclasses 13+ and 85+ for time correction, and subclasses 21+ and 113+ for recorder or reproducer fault condition compensation.

Read-in with read-out and compare:
This subclass is indented under subclass 718. Subject matter
in which the testing is done by reading in a test pattern, reading out the contents of the memory and comparing the output with the test pattern read in.

Special test pattern (e.g., checkerboard, walking ones):
This subclass is indented under subclass 719. Subject matter in which the test patterns are selected to exercise the memory by transferring a combination of logic zeroes and ones through the memory, e.g., alternating zeroes and ones-checkerboard pattern.

Electrical parameter (e.g., threshold voltage):
This subclass is indented under subclass 718. Subject matter in which the diagnostic test measures an electrical parameter of the memory device, e.g., threshold voltage.

Performing arithmetic function on memory contents:
This subclass is indented under subclass 718. Subject matter in which the diagnostic test consists of performing an arithmetic function, such as addition, on the contents of the memory and comparing the results to a reference value.

Error mapping or logging:
This subclass is indented under subclass 718. Subject matter in which the detected error or fault is registered or recorded to present a history for diagnostic purposes.

SEE OR SEARCH THIS CLASS, SUBCLASS:
42 for such subject matter used with data processor testing.

DIGITAL LOGIC TESTING:
This subclass is indented under the class definition. Subject matter in which the diagnostic test is performed upon a system or element performing a binary logic operation upon a signal having plural distinct discrete states.
(1) Note. Testing or measuring of electrical properties are classified elsewhere unless the testing device includes analysis of the information content of a digital signal. Control signals are not data signals.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, appropriate subclass, particularly subclass 73 for measuring and testing of electrical device parameters under controlled conditions.
326, Electronic Digital Logic Circuitry, subclass 16 for electronic digital logic circuitry with test facilitating feature and subclasses 21+ for electronic digital logic circuitry maintaining signal integrity.

Programmable logic array (PLA) testing:
This subclass is indented under subclass 724. Subject matter for testing an array of logical elements selectively configurable to sequentially perform various binary logic functions.
(1) Note. Examples of such binary logic functions are AND, OR, NAND, NOR, and NOT.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, appropriate subclass, particularly subclass 73.1 for measuring and testing of electrical device parameters under controlled conditions.
326, Electronic Digital Logic Circuitry, subclass 16 for electronic digital logic circuitry with test facilitating feature, subclasses 21+ for electronic digital logic circuitry maintaining signal integrity, and subclasses 37+ for a programmable or multifunctional logic array circuit, per se.

Scan path testing (e.g., level sensitive scan design (LSSD)):
This subclass is indented under subclass 724. Subject matter in which digital logic is designed for improved testability by including shift register latches (SRL) to enable the configuring of the circuitry into combinational logic form.
(1) Note. Test data is clocked (scanned) through the combinational logic forms and then compared to a reference.

SEE OR SEARCH THIS CLASS, SUBCLASS:
738 for digital logic testing including test pattern generation in general.

SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, subclass 16 for logic circuitry with test feature.
377, Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems, appropriate subclasses for shift register latches, per se.

Boundary scan:
This subclass is indented under subclass 726. Subject matter where selected components in a circuit are each provided with one or more cells, comprising a single-bit register, coupled to a node of a component, such as an input, output, input/output or control node, and where said cells are serially coupled in a single chain, usually referred to as a boundary-scan chain.

Random pattern generation (includes pseudorandom pattern)
This subclass is indented under subclass 726. Subject matter where a series of digits is generated in an unpredictable, incoherent, or arbitrary pattern.
(1) Note. Included herein is generation of a series of digits which simulates a random pattern.

SEE OR SEARCH THIS CLASS, SUBCLASS:
715 for test pattern with comparison in testing a transmission facility.
720 for use of special test patterns in memory testing.
739 for random test pattern generation in general.

SEE OR SEARCH CLASS:
708, Electrical Computers and Digital Processing Systems-Arithmetic Processing and Calculating, 250 for random number generation.

Plural scan paths:
This subclass is indented under subclass 726. Subject matter having more than one group of shift register latches connected in series, and which groups form a plurality of shift paths (scan paths) along which data can be transmitted.

Addressing:
This subclass is indented under subclass 726. Subject matter including data which specifies a location.

SEE OR SEARCH THIS CLASS, SUBCLASS:
743 for addressing in digital logic testing using a test pattern generator.

SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, 230.01 for addressing memories.
711, Electrical Computers and Digital Processing Systems-Memory, 200 for address formation in data processing systems.

Clock or synchronization:
This subclass is indented under subclass 726. Subject matter including a reference timing function or a clock-pulse generator for causing the various parts of the device to operate on a common time base.

SEE OR SEARCH THIS CLASS, SUBCLASS:
744 for clock or synchronization in digital logic testing
using a test pattern generator.

SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, 93 for clocking or synchronization of logic stages or gates.
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, 141 for synchronizing electrical nonlinear devices.
713, Electrical Computers and Digital Processing Systems-Support, subclasses 400-503 for synchronization in computer systems.

Signature analysis:
This subclass is indented under subclass 724. Subject matter controlled including monitoring of controlled conditions of execution test points or nodes within the digital logic device and the measured output (signature) is compared to a known good signature.

Built-in test circuit (BILBO):
This subclass is indented under subclass 724. Subject matter in which the digital logic testing equipment includes a selectively configurable shift register, structurally a part of the device being tested.
(1) Note. Some selective configurations of the shift register include a latch, linear shift register, multiple input signature register, and a forced reset.
(2) Note. Included herein are built-in logic block observation (BILBO) devices.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, appropriate subclass, particularly subclass 73.1 for measuring and testing of electrical device parameters under controlled conditions.
377, Electrical Pulse Counters, Pulse Dividers, or Shift Registers, 19 for a shift register used for measuring or testing; and subclass 28 for error checking or correction in a shift register system.

Structural (in-circuit test):
This subclass is indented under subclass 724. Subject matter in which each component of the logic circuit is tested individually while physically connected to the circuit.
(1) Note. Generally, the test instrument is connected to nodes of the logic circuit under test in a unique way for each component.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, appropriate subclass, particularly subclass 73.1 for measuring and testing of electrical device parameters (other than by information signal content) under controlled conditions.

Device response compared to input pattern:
This subclass is indented under subclass 724. Subject matter in which the operational condition of a system or device is determined by comparing the system or device response to a test signal input pattern.

Device response compared to expected fault-free response:
This subclass is indented under subclass 724. Subject matter in which the operational condition of a system or device is determined by comparing the system or device response to a predetermined fault-free response.

Device response compared to fault dictionary/truth table:
This subclass is indented under subclass 724. Subject matter in which the operational condition and identification of an actual or potential fault is determined by comparing the system response to a predetermined fault dictionary or truth table.

Including test pattern generator:
This subclass is indented under subclass 724. Subject matter in which the specific means or method of generating a test pattern for a digital logic testing system is claimed.

SEE OR SEARCH CLASS:
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, 100 for miscellaneous waveform generationor conversion.
345, Selective Visual Display Systems, subclass 26 and 194+ for a character generator in a visual display system with selective electrical control.
708, Electrical Computers and Digital Processing Systems-Arithmetic Processing and Calculating, 250 for random number generators, and subclasses 270+ for digital function generators.

Random pattern generation (includes pseudorandom pattern):
This subclass is indented under subclass 738. Subject matter where a series of digits is generated in an unpredictable, incoherent or arbitrary pattern.
(1) Note. Included herein is generation of a series of digits which simulates a random pattern.

SEE OR SEARCH THIS CLASS, SUBCLASS:
715 for testing a transmission facility using a test pattern with comparison
720 for use of special test patterns in memory testing.
728 for random test pattern generation in boundary scanning.

SEE OR SEARCH CLASS:
708, Electrical Computers and Digital Processing Systems-Arithmetic Processing and Calculating, 250 for random number generation.

Having analog signal:
This subclass is indented under subclass 738. Subject matter including an electrical signal, the amplitude or frequency of which varies continuously in value over time.

Simulation:
This subclass is indented under subclass 738. Subject matter having an electrical model or a computer program which imitates the operation of a device under test.

SEE OR SEARCH CLASS:
395, Information Processing System Organization, 500.24 for electrical analog simulator, subclasses 500.27+ for simulating nonelectrical device or system, and subclasses 500.34+ for simulating electronic device and electrical system.

Testing specific device:
This subclass is indented under subclass 738. Subject matter where the test pattern is applied to a distinctive named means to carry out a special function.
(1) Note. Examples of things that are not specific devices include "logic device," "circuit," "device under test," etc.
(2) Note. See sections D and E of the class definition for the distinction between this class and classes having the specific device.

SEE OR SEARCH THIS CLASS, SUBCLASS:
718 for testing an information signal storage device.

Addressing:
This subclass is indented under subclass 738. Subject matter including data which specifies a location.

SEE OR SEARCH THIS CLASS, SUBCLASS:
730 for scan path testing with addressing.

SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, 230.01 for addressing memories.
711, Electrical Computers and Digital Processing Systems-Memory, 1 and 200+ for memory address formation in data processing systems.

Clock or synchronization:
This subclass is indented under subclass 738. Subject matter including a reference timing function or a clock pulse generator for causing the various parts of the device to operate on a common time base.

SEE OR SEARCH THIS CLASS, SUBCLASS:
731 for clocking or synchronizing in scan path testing.

SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, 93 for clocking or synchronizing of logic stages or gates.
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, 141 for synchronizing nonlinear devices, circuits, or systems.
713, Electrical Computers and Digital Processing Systems-Support, subclasses 400-503 for synchronization in computer systems.

Determination of marginal operation limits:
This subclass is indented under subclass 724. Subject matter in which the device or system is tested under controlled and varying circuit parameters, such as input voltage, to determine the range of circuit parameter values within which the device or system operates without error or malfunction.

DIGITAL DATA ERROR CORRECTION:
This subclass is indented under the class definition. Subject matter in which the error in information content of
pulse or pulse coded data is corrected.

SEE OR SEARCH THIS CLASS, SUBCLASS:
799 for error detection which does not include correction of the error signal.

Substitution of previous valid data:
This subclass is indented under subclass 746. Subject matter in which a previously validated data state or value is substituted for data state or value determined to be erroneous.

Request for retransmission:
This subclass is indented under subclass 746. Subject matter in which the digital data error correction is achieved by retransmission of data responsive to a request.

Retransmission if no ACK returned:
This subclass is indented under subclass 748. Subject matter in which a retransmission of data is initiated upon the condition that no acknowledgment (ACK) signal is returned from the receiver.

Feedback to transmitter for comparison:
This subclass is indented under subclass 748. Subject matter in which the digital data is returned to the transmitter for comparison to detect an error.

Including forward error correcting capability:
This subclass is indented under subclass 748. Subject matter in which the digital data is encoded to enable error
correction at the receiver and retransmission is requested only if the error rate exceeds the forward error correcting capability.

Forward correction by block code:
This subclass is indented under subclass 746. Subject matter in which a grouping of symbols (i.e., a block of data or a data word) is transformed into a code word having an increased number of symbols in order to provide an increased minimum distance between code words relative to the minimum distance of the corresponding data words in order to provide for forward correction of the encoded data in the event that an error or erasure is subsequently imposed on the encoded data.
(1) Note. This subclass includes both forward error correction, per se, (i.e., the receiver corrects the error without requiring any further information from the sender, which requires a minimum amount of redundancy in the transmission since not only must an error be detected, but its location must be determined) and forward error correction with the assistance of symbol reliability information.
(2) Note. Forward error correction (FEC) is an error-correcting technique that avoids the need for any reverse channel by enabling self-correction of errors at the receiver by adding information (at the expense of throughput) to enable the receiver to determine what the error was and the correct information to substitute for said error.

SEE OR SEARCH THIS CLASS, SUBCLASS:
786 for convolutional codes in which each check bit is generated as a function of a different plurality of information bits and is interspersed among the information bits at predetermined intervals with no natural beginning point or ending point.

Double error correcting with single error correcting code:
This subclass is indented under subclass 752. Subject matter in which a single bit error correcting code arrangement corrects double bit errors by successively correcting consecutive single bit errors.

Error correction during refresh cycle:
This subclass is indented under subclass 752. Subject matter including a digital data storage device having a refresh cycle in which decaying information is read before it becomes unrecognizable, and rewritten in original form, and decoding a stored block data code signal for error correction during the refresh cycle.

Double encoding codes (e.g., product, concatenated):
This subclass is indented under subclass 752. Subject matter including calculation and independent decoding of two independent sets of check words for enhancement of error correction.

Cross-interleave Reed-Solomon code (CIRC):
This subclass is indented under subclass 755. Subject matter doubly encoded with Reed-Solomon codes and interleaved to enable the correction of burst errors.

Parallel generation of check bits:
This subclass is indented under subclass 752. Subject matter having plural check bit calculating elements connected in parallel.

Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity):
This subclass is indented under subclass 752. Subject matter which encodes digital data with both an error correcting code (ECC) for error correction and detection, and an additional error detection code to detect uncorrected errors.
(1) Note. Such additional codes include a cyclic redundancy code (CRC) and a parity bit code.

Look-up table encoding or decoding:
This subclass is indented under subclass 752. Subject matter having an encoder or decoder which contains a table of all possible error patterns in a corrupted received code word and compares the computed syndrome to these patterns to determine the position of erroneous bits.

Threshold decoding (e.g., majority logic):
This subclass is indented under subclass 752. Subject matter the decoder operates upon a corrupted received code word to compute the parity check sums which are applied to a threshold or majority gate and an error indicated if the sums exceed a certain value.

Random and burst error correction:
This subclass is indented under subclass 752. Subject matter in which the block code is capable of correcting both random and burst errors.
(1) Note. Random errors are of the type where each data bit is affected independently by noise. Burst errors are of the type where disturbances introduce errors of unspecified time duration and thus cause a cluster of multiple consecutive data bits in error.
(2) Note. Interlacing or interleaving techniques may be used to give a random error correcting code the capability of correcting both random and burst errors. A product code or concatenated code may be formed from two codes to provide both random and burst error correction capability.

Burst error correction:
This subclass is indented under subclass 752. Subject matter in which the block code is derived to be most effective in correcting burst errors.
(1) Note. An example of a block code with good burst-correcting capability is the Reed-Solomon code.
Interleaving techniques are also utilized to improve the burst-correcting capability of a code.

Memory access:
This subclass is indented under subclass 752. Subject matter in which digital data being written into or read out of a storage device is encoded in a block code format.

SEE OR SEARCH THIS CLASS, SUBCLASS:
710 for memory fault recovery systems.
718 for diagnostic testing of a memory.

SEE OR SEARCH CLASS:
360, Dynamic Magnetic Information Storage or Retrieval, subclass 26, 36.1+, 47, and 53 for error detection combined with a magnetic, dynamic memory system.
365, Static Information Storage and Retrieval, subclass 200 and 201 for bad bit and testing read/write circuits, respectively.
369, Dynamic Information Storage or Retrieval, appropriate subclasses for a dynamic, nonmagnetic memory device.

Error correct and restore:
This subclass is indented under subclass 763. Subject matter which corrects the errors upon readout of the data and the corrected data in written into memory as a substitute for the erroneous data.

Error pointer:
This subclass is indented under subclass 763. Subject matter which generates a signal (pointer) upon the occurrence of a particular type of error or failure.
(1) Note. In many error correcting systems accessing data from a memory or storage device, the error pointer identifies the track or channel with which the error or failure is associated.

Check bits stored in separate area of memory:
This subclass is indented under subclass 763. Subject matter including a section of memory for storage of the check bits separate from that the section of memory storing data information.

Code word for plural n-bit (n>1 ) storage units (e.g., x 4 DRAM's):
This subclass is indented under subclass 763. Subject matter in which there is more than one storage device, each storing more than a single digit of data.

Error correction code for memory address:
This subclass is indented under subclass 763. Subject matter where the block code includes a memory address as part of the encoded data.

Dynamic data storage:
This subclass is indented under subclass 763. Subject matter where there is relative motion between a transducer and an information storage medium.

SEE OR SEARCH CLASS:
360, Dynamic Magnetic Information Storage or Retrieval, for dynamic magnetic data storage and retrieval.
369, Dynamic Information Storage or Retrieval, for dynamic data storage and retrieval.

Disk array:
This subclass is indented under subclass 769. Subject matter where the storage medium is a plurality of interconnected disks.

Tape:
This subclass is indented under subclass 769. Subject matter where the storage medium is essentially of a two dimensional shape with one dimension being very long in relation to the other.

Code word parallel access:
This subclass is indented under subclass 763. Subject matter in which the bits of the code word are created from parallel data digits.

Solid state memory:
This subclass is indented under subclass 763. Subject matter where the storage device is or contains a solid state device (e.g., an integrated circuit or transistor).

SEE OR SEARCH THIS CLASS, SUBCLASS:
718 for memory testing.

SEE OR SEARCH CLASS:
65, Static Information Storage and Retrieval, 174 for solid state memories.

Adaptive error-correction capability:
This subclass is indented under subclass 752. Subject matter in which the error-correction capability of the system is adapted to the existing error rate by selection of encoding format.

Synchronization:
This subclass is indented under subclass 752. Subject matter in which a lack of synchronization between encoder and decoder is detected and/or corrected.

For packet or frame multiplexed data:
This subclass is indented under subclass 752. Subject matter where plural encoded data streams are simultaneously transmitted over a common transmission medium in such a manner that the information signals may be discretely recovered, wherein each data stream contains one or more bytes preceded by an address header or where the simultaneously transmitted plurality of data streams include synchronization or other control information.

SEE OR SEARCH CLASS:
370, Multiplex Communications, 351 for multiplex switching such as packet or frame switching.

Hamming code:
This subclass is indented under subclass 752. Subject matter where there are m information code elements and k error check code elements such that there are sufficient check elements to correct a single error and the k check elements are determined by even parity checks in conjunction with element values appearing in certain selected information positions where each of the elements of the code group must be in a parity check subgroup with one or more of the check elements and no two different code elements having exactly the same set of check elements associated with it.
(1) Note. See U.S. Patent RE23601, columns 5-9, for a more rigorous definition.

Nonbinary data (e.g., ternary):
This subclass is indented under subclass 752. Subject matter where each bit of a data word can assume more than two values.

SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, 59 for nonbinary logic circuits.

Variable length data:
This subclass is indented under subclass 752. Subject matter where the number of bits in a data word is not fixed, but can vary from word to word.

Using symbol reliability information (e.g., soft decision):
This subclass is indented under subclass 752. Subject matter where, during error correction, in addition to an error correcting code, use is made of information about the reliability of the decoding of a particular bit.

Code based on generator polynomial:
This subclass is indented under subclass 752. Subject matter where a code word c(x), where x is a unit delay operator, is generated by dividing a delayed version of the data polynomial d(x), i.e.,. xnd(x), by a generator polynomial, g(x), and subtracting the remainder from the delayed version of the data polynomial, thereby producing a code word that is a multiple of the generator polynomial, and where the data polynomial d(x) is such that positions within the block correspond to powers of x and data values at the positions correspond to polynomial coefficient values.

Bose-Chaudhuri-Hocquenghem code:
This subclass is indented under subclass 781. Subject matter where the block code is a t error correcting code which is the set of all polynomials {a(c)} over the Galois field GF( 2m) of degree n-1 or less, such that a(ai)=0, for i=1,3,5,..., 2t-1 where a is a primitive element of the finite field GF( 2m), and where c is the radix 2 for binary data, a(c)=a0+a1c+a2c2+...+an-1cn - 1, and aj=0,1
(j=0,1,2,..., n-1 ).

Golay code:
This subclass is indented under subclass 781. Subject matter where the block code is an (n, k, t) type polynomial code in which each code word is n=23 bits long, contains k=13 data or information bits, corrects up to t=3 errors, and the code word also contains (n-k)=10 redundant check bits.

Reed-Solomon code:
This subclass is indented under subclass 781. Subject matter where the block code consists of K data and N-K check symbols, where N is an arbitrary number and K is less than N, and where each symbol is made of J binary bits encoded with a generator polynomial g(x) for the code and a field generating polynomial M(x) which defines the Galois field.

SEE OR SEARCH THIS CLASS, SUBCLASS:
756 for cross-interleave Reed-Solomon codes.
762 for burst error correction using Reed-Solomon codes.

Syndrome computed:
This subclass is indented under subclass 781. Subject matter where decoded data is divided by an inverse of the generator polynomial to obtain a data word of 1 bit which indicate which bits of the decoded data are in error.

Forward error correction by tree code (e.g., convolutional):
This subclass is indented under subclass 746. Subject matter in which information bits are encoded to generate a plurality of check bits, each check bit is generated as a function of a different plurality of information bits and is interspersed among the information bits at predetermined intervals with no natural beginning point or ending point (i.e., there is no length restriction for the encoded data).
(1) Note. Convolutional coding means adding to the information a repeating sequence that is known to the receiver. By subtracting this repeating sequence and performing other tests, the receiver can determine what should have been received with a high degree of accuracy.
(2) Note. This subclass includes forward error correction, per se, (i.e., the receiver corrects the error without requiring any further information from the sender, which requires a minimum amount of redundancy in the transmission since not only must an error be detected, but its location must be determined) and forward error correction with the assistance of symbol reliability information.
(3) Note. This subclass does not include demodulation decisions based upon oversampling or on intersymbol interference alone.
(4) Note. This subclass does not include channel equalization or predistortion control based on correction results (e.g., decision feedback equalization).
(5) Note. This subclass does not include detection or correction of errors produced by trial values, perturbations, predictions, quantizations, estimations or approximations, which errors are used as feedback for control of signal generation or coding (e.g., PID controlling, source calibration, successive approximation A/D conversion, DSV constrained encoding, predictive encoding).
(6) Note. Forward error correction (FEC) is an error-correcting technique that avoids the need for any reverse channel by enabling self-correction of errors at the receiver by adding information (at the expense of throughput) to enable the receiver to determine what the error was and the correct information to substitute for said error.

SEE OR SEARCH THIS CLASS, SUBCLASS:
746 and 797, for various types of data correction such as trial values, perturbations, predictions, quantizations, estimations or approximations, which errors are used as feedback for control of signal generation or coding.
752 for block codes wherein the information bits and associated bits form independent and distinct blocks of data bits.
799 for various error/fault detection techniques such as those based on oversampling or intersymbol interference.

SEE OR SEARCH CLASS:
341, Coded Data Generation or Conversion, 50 for digital data conversion and subclasses 126+ for analog to or from digital conversion.
375, Pulse or Digital Communications,229 for pulse or digital equalizers.

Random and burst errors:
This subclass is indented under subclass 786. Subject matter in which the convolutional code is capable of correcting both random and burst errors.

SEE OR SEARCH THIS CLASS, SUBCLASS:
761 for block code correction of both random and burst errors.

Burst error:
This subclass is indented under subclass 786. Subject matter in which the convolutional code corrects for burst error.

SEE OR SEARCH THIS CLASS, SUBCLASS:
762 for block code correcting of burst errors.

Synchronization:
This subclass is indented under subclass 786. Subject matter in which a lack of synchronization between the encoder and decoder is detected and/or corrected.

Puncturing:
This subclass is indented under subclass 786. Subject matter where single bits are periodically deleted at intervals from a low-rate convolutional code.

Sequential decoder (e.g., Fano or stack algorithm):
This subclass is indented under subclass 786. Subject matter where a tree structure of the convolutional code is used for searching locally a path which is considered to be the most likely to produce a correct data sequence.

SEE OR SEARCH THIS CLASS, SUBCLASS:
794 for maximum likelihood decoding in general.
796 for branch metric calculation in general.

Trellis code:
This subclass is indented under subclass 786. Subject matter where, for a convolutional code of k bits length, an inverse coding operation is performed in which 2k-1 decision bits are used to select an output bit and where after many branches, the most probable path will be selected with a high degree of certainty, and where the branches form a mesh pattern (i.e., branches start at a plurality of points and intersect other branches).

SEE OR SEARCH CLASS:
375, Pulse or Digital Communications, subclass 265 for trellis coders and decoders in pulse or digital communication.
704, Data Processing: Speech Signal Processing, Linguistics, Language Translation, and Audio Compression/Decompression, subclass 242 for Viterbi trellis speech recognition.

Syndrome decodable (e.g., self orthogonal):
This subclass is indented under subclass 786. Subject matter where decoded data is divided by an inverse of the generator polynomial to obtain a data word of 1 bit which indicate which bits of the decoded data are in error.

SEE OR SEARCH THIS CLASS, SUBCLASS:
785 for syndrome decodable block codes.

Maximum likelihood:
This subclass is indented under subclass 786. Subject matter where a decoder selects the sequence out of all the possible transmitted sequences which is most likely to match the received data sequence and determines corresponding digital (data) information.

SEE OR SEARCH THIS CLASS, SUBCLASS:
791 for a sequential decoder.
795 for Viterbi decoding.

SEE OR SEARCH CLASS:
375, Pulse or Digital Communications, subclass 262 and 341 for maximum likelihood decoding (other than for error correction) in pulse or digital communication.

Viterbi decoding:
This subclass is indented under subclass 786. Subject matter where data is not decoded as soon as it is received, instead, a sequence of data, having a predetermined decoding depth, following the digit to be decoded is first collected, then, by computing what are known as path metrics, a limited number of possible messages are selected, each extending throughout the decoding depth far beyond the digit presently to be decoded, with one such survivor sequence ending in each of the data states.

SEE OR SEARCH THIS CLASS, SUBCLASS:
794 for maximum likelihood decoding.
796 for branch metric calculation decoding.

SEE OR SEARCH CLASS:
375, Pulse or Digital Communications, subclass 262 and 341 for Viterbi decoding (other than for error correction) in pulse or digital communication.
704, Data processing-Speech Signal Processing, Linguistics, Language Translation, and Audio Compression/Decompression, subclass 242 for Viterbi trellis speech recognition.

Branch metric calculation:
This subclass is indented under subclass 786. Subject matter where a tree of possible data sequences is constructed identifying the possible data sequences in terms of data states, and from which correlations are computed for selecting the paths which are to survive to the next stage of decoding received data.

SEE OR SEARCH THIS CLASS, SUBCLASS:
791 for sequential decoding.
795 for Viterbi decoding.

Majority decision/voter circuit:
This subclass is indented under subclass 746. Subject matter in which error correction is effectively achieved by error masking (making error invisible at output) through majority logic or voting techniques.

SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, 35 for threshold (e.g., majority) logic.

ERROR DETECTION FOR SYNCHRONIZATION CONTROL:
This subclass is indented under the class definition. Subject matter in which error detecting techniques are utilized to detect an out-of-synch condition or to control synchronization between devices.

SEE OR SEARCH THIS CLASS, SUBCLASS:
775 for block code synchronization error correction.
789 for convolutional code synchronization error correction.

SEE OR SEARCH CLASS:
370, Multiplex Communications, 503 for synchronization of time multiplex information which may include error detecting techniques.
375, Pulse or Digital Communications, subclass 357 for synchronization failure prevention in pulse or digital communication.

ERROR/FAULT DETECTION TECHNIQUE:
This subclass is indented under the class definition. Subject matter in which a specific technique is recited for detecting an error or fault condition.

SEE OR SEARCH THIS CLASS, SUBCLASS:
1 for reliability and availability, fault recovery, locating, and avoidance in digital data processing systems.
746 for digital data error correction which include error/fault detection techniques.

Parity bit:
This subclass is indented under subclass 799. Subject matter in which a redundant bit is added to a block of data bits.
(1) Note. This redundant bit or parity bit is of a logic state to make the total number of bits having a predetermined logic state within the block odd or even.

Parity generator or checker circuit detail:
This subclass is indented under subclass 800. Subject matter which specify the particular elements of a parity signal source or comparator circuit.

Even and odd parity:
This subclass is indented under subclass 800. Subject matter wherein the parity scheme in the system includes the generation of parity bits on both an even and odd basis.

Parity prediction:
This subclass is indented under subclass 800. Subject matter which calculates an expected parity value prior to execution of an operation and is subsequently compared to the actual parity value to detect an error.

Plural dimension parity check:
This subclass is indented under subclass 800. Subject matter in which a single parity bit is derived from data bits taken over each of two or more dimensions, such as horizontal and vertical parity.

Storage accessing (e.g., address parity check):
This subclass is indented under subclass 800. Subject matter in which the parity bit is calculated for data bits read into or read out of an information signal storage device. (1) Note. Address parity check arrangements are included in this subclass.

Constant-ratio code (m/n):
This subclass is indented under subclass 799. Subject matter in which a code constraint of a constant-ratio between bits of a first logic state and a second logic state is utilized to enable error/fault detection.

Check character:
This subclass is indented under subclass 799. Subject matter in which a check character, derived as a predetermined function of a group of data bits, is associated with the group of data bits for error detection purposes.

Modulo-n residue check character:
This subclass is indented under subclass 807. Subject matter
in which a check character, calculated as the remainder after the value of the digital data is divided by a modulus-n, is associated with the digital data to enable error/fault detection.

SEE OR SEARCH CLASS:
708, Electrical Computers-Arithmetic Processing and Calculating, subclass 532 for residue code checking in arithmetic operations.

Code constraint monitored:
This subclass is indented under subclass 799. Subject matter in which the digital data encoding scheme provides inherent constrained conditions which are monitored to enable error/fault detection.

Multilevel coding (n>2 ):
This subclass is indented under subclass 809. Subject matter in which the digital data is encoded in a multilevel or multistate format where the number of levels or states is greater than 2.

SEE OR SEARCH CLASS:
375, Pulse or Digital Communications, subclass 292 for disparity reduction in multilevel digital communications.

Forbidden combination or improper condition:
This subclass is indented under subclass 799. Subject matter in which a forbidden combination of digital data or improper condition of a device is monitored to enable error or fault detection.

Specified digital signal pattern or pulse count:
This subclass is indented under subclass 811. Subject matter in which the forbidden combination is either a specified
pattern of digital data or a count of one or more types of digital pulses.

Two key-down detector:
This subclass is indented under subclass 811. Subject matter in which the improper condition is the simultaneous activation of two or more keys on a data input device.

Data timing/clocking:
This subclass is indented under subclass 811. Subject matter in which the timing or clocking of digital data is monitored to detect a predetermined forbidden combination or condition.

Time delay/interval monitored:
This subclass is indented under subclass 811. Subject matter in which the time delay between events or data is detected to determine a predetermined forbidden condition.

Two-rail logic:
This subclass is indented under subclass 811. Subject matter in which both the true and complement state of each logic function is provided and the simultaneous occurrence of both states indicates a forbidden combination.

Noise level:
This subclass is indented under subclass 811. Subject matter in which the forbidden condition is the presence of noise exceeding a predetermined level.

Missing-bit/drop-out detection:
This subclass is indented under subclass 811. Subject matter in which the improper combination is a missing bit or dropout of a bit within a data character.

SEE OR SEARCH CLASS:
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, 18 for missing pulse detecting means.
386, Television Signal processing for Dynamic Recording or Reproducing, 2 and 47+ for drop-out detecting or correcting in the processing of a television signal.

Comparison of data:
This subclass is indented under subclass 799. Subject matter in which an error or fault is detected by the comparison of data.

SEE OR SEARCH THIS CLASS, SUBCLASS:
735 for diagnostic apparatus testing which include error detection by comparison of data.

SEE OR SEARCH CLASS:
340, Communications: Electrical, subclass 146.2 for digital comparator devices, per se.

Plural parallel devices or channel:
This subclass is indented under subclass 819. Subject matter in which the data from plural parallel devices or channels is compared to detect an error or fault.

Transmission facility:
This subclass is indented under subclass 820. Subject matter which detects an error or fault in a device including a channel of a transmission medium with a device for supplying
a digital signal thereto.

Sequential repetition:
This subclass is indented under subclass 819. Subject matter in which an error or fault is detected by comparison of repetitive data.
(1) Note. Included herein is majority logic or voter circuitry in which the most frequently occurring data is presumed to be correct.

True and complement data:
This subclass is indented under subclass 822. Subject matter in which the data being transferred and compared comprises both the true and complement bit states of the data.

Device output compared to input:
This subclass is indented under subclass 819. Subject matter in which the error/fault detection is enabled by comparing the device output with the device input.

SEE OR SEARCH THIS CLASS, SUBCLASS:
735 for diagnostic apparatus testing which includes comparison of the device output with the device input.

MISCELLANEOUS:
This subclass is indented under the class definition. Subject matter not hereinabove classified.

Scan path testing (LSSD): Foreign art collections including subject matter in which digital logic is designed for improved test ability by including shift register latches (SRL) to enable the configuring of the circuitry in combinational logic form.

Including test pattern generator: Foreign art collections including subject matter in which the specific means or method of generating a test pattern for an error checking system is claimed.

Block code: Foreign art collections including subject matter in which a plurality of information bits are encoded to generate a plurality of check bits as a function of the information bits with the information bits and check bits being associated together to form a block code.

Memory access: Foreign art collections including subject matter in which digital data being written into or read out of a storage device is encoded in a block code format.

Convolutional code: Foreign art collections including subject matter in which the information bits are encoded to generate a plurality of check bits, each check bit is generated as a function of a different plurality of information bits and is interspersed among the information bits at predetermined intervals with no natural beginning point or ending point as in block codes.

SKEW DETECTION/CORRECTION: Foreign art collections including subject matter in which an error caused by the time delay between plural parallel bits forming a byte or data word is detected and/or corrected.

DATA FORMATTING TO IMPROVE ERROR DETECTION/CORRECTION CAPABILITY: Foreign art collections including subject matter in which a change in data format or sequence is utilized to improve the error detection/correction capability of a coding scheme.

Memory access (e.g., address permutation): Foreign art collections including subject matter which changes the format of digital data by having the signal with the data written into or read out of a storage device.

TESTING OF ERROR-CHECK SYSTEM: Foreign art collections including subject matter in which the proper operation of the error detection/correction or fault detection/recovery apparatus itself is verified.

Error count or rate: Foreign art collections including subject matter which determines the number of bits in error or the number of bits in error per unit of time.

Pseudo-error rate: Foreign art collections including subject matter having a main data path and a secondary data path having intentionally degraded performance connected in parallel, the secondary path having a decision device to compare and evaluate the disagreement between the paths.

Up-down counter: Foreign art collections including subject matter including an reversible accumulating register which counts up in response to an error and counts down in response to an error-free increment of time.

Synchronization control: Foreign art collections including subject matter in which a determination of the error rate is used to control synchronization between devices.

Shutdown or establishing system parameter (e.g., transmission rate): Foreign art collections including subject matter including control of system operation by either deactivation of the system, or controls a parameter related to normal system operation, in response to error count or error rate.

DATA PULSE EVALUATION/BIT DECISION: Foreign art collections including subject matter in which the information bearing parameter (amplitude, pulse position, etc.) of a data pulse is evaluated to determine the proper logic state or value.

REPLACEMENT OF MEMORY SPARE LOCATION, PORTION, OR SEGMENT: Foreign art collections including subject matter in which the spare apparatus comprises only a location, or a contiguous group of locations of memory.

Spare row or column: Foreign art collections including subject matter in which a spare apparatus comprises only a column or row within a memory device or element.

TRANSMISSION FACILITY TESTING: Foreign art collections including subject matter in which the diagnostic testing is performed upon a channel of a transmission medium with a device for supplying digital data thereto.

For channel having repeater: Foreign art collections including subject matter wherein a transmission channel has a
repeating amplifier.

By tone signal: Foreign art collections including subject matter which includes application of a test signal composed of one or more tone signals.

Test pattern with comparison: Foreign art collections including subject matter in which the transmission facility is tested by applying a test pattern to the device under test and comparing the output to a reference test pattern.

Loop-back: Foreign art collections including subject matter in which the transmission facility is configured so that the receiver shunts the test pattern back to transmitter for comparison at the transmitter.

Loop or ring configuration: Foreign art collections including subject matter in which a plurality of transmission stations or devices are configured in a serial fashion to form a loop or ring.

MEMORY TESTING: Foreign art collections including subject matter in which the diagnostic testing is performed upon an information signal storage device.

Read-in with read-out and compare: Foreign art collections including subject matter in which the testing is done by reading in a test pattern, reading out the contents of the memory and comparing the output with the test pattern read in.

Special test patterns (e.g., checkerboard, walking ones): Foreign art collections including subject matter in which the test patterns are selected to exercise the memory by transferring a combination of logic zeroes and ones through the memory, e.g., alternating zeroes and ones-checkerboard pattern.

Electrical parameters (e.g., threshold voltage): Foreign art collections including subject matter in which the diagnostic test measures an electrical parameter of the memory device, e.g., threshold voltage.

Performing arithmetic functions on memory contents: Foreign art collections including subject matter in which the diagnostic test consists of performing an arithmetic function, such as addition, on the contents of the memory and comparing the results to a reference value.

Error mapping or logging: Foreign art collections including subject matter in which the detected error or fault is registered or recorded to present a history for diagnostic purposes.

DIGITAL LOGIC TESTING: Foreign art collections including subject matter in which the diagnostic test is performed upon a system or element performing a binary logic operation upon a signal having plural distinct discrete states.

Programmable logic array (PLA) testing: Foreign art collections including subject matter for testing an array of logical elements selectively configurable to sequentially perform various binary logic functions.

Scan path testing (e.g., level sensitive scan design (LSSD)): Foreign art collections including subject matter in which digital logic is designed for improved testability by including shift register latches (SRL) to enable the configuring of the circuitry into combinational logic form.

Boundary scan: Foreign art collections including subject matter where selected components in a circuit are each provided with one or more cells, comprising a single-bit register, coupled to a node of a component, such as an input, output, input/output or control node, and where said cells are serially coupled in a single chain, usually referred to as a boundary-scan chain.

Random pattern generation (includes pseudorandom pattern): Foreign art collections including subject matter where a series of digits is generated in an unpredictable, incoherent, or arbitrary pattern.

Plural scan paths: Foreign art collections including subject matter having more than one group of shift register latches connected in series, and which groups form a plurality of shift paths (scan paths) along which data can be transmitted.

Addressing: Foreign art collections including subject matter including data which specifies a location.

Clock or synchronization: Foreign art collections including subject matter including a reference timing function or a clock-pulse generator for causing the various parts of the device to operate on a common time base.

Signature analysis: Foreign art collections including subject matter controlled including monitoring of controlled conditions of execution test points or nodes within the digital logic device and the measured output (signature) is compared to a known good signature.

Built-in test circuit (BILBO): Foreign art collections including subject matter in which the digital logic testing equipment includes a selectively configurable shift register, structurally a part of the device being tested.

Structural (in circuit test): Foreign art collections including subject matter in which each component of the logic circuit is tested individually while physically connected to the circuit.

Device response compared to input pattern: Foreign art collections including subject matter in which the operational condition of a system or device is determined by comparing the system or device response to a test signal input pattern.

Device response compared to expected fault-free response: Foreign art collections including subject matter in which the operational condition of a system or device is determined by comparing the system or device response to a predetermined fault-free response.

Device response compared to fault dictionary/truth table: Foreign art collections including subject matter in which the operational condition and identification of an actual or potential fault is determined by comparing the system response to a predetermined fault dictionary or truth table.

Including test pattern generator: Foreign art collections including subject matter in which the specific means or method of generating a test pattern for a digital logic testing system is claimed.

Random pattern generation (includes pseudorandom pattern): Foreign art collections including subject matter where a series of digits is generated in an unpredictable, incoherent or arbitrary pattern.

Having analog signal: Foreign art collections including subject matter including an electrical signal, the amplitude or frequency of which varies continuously in value over time.

Simulation: Foreign art collections including subject matter having an electrical model or a computer program which imitates the operation of a device under test.

Testing specific device: Foreign art collections including subject matter where the test pattern is applied to a distinctive named means to carry out a special function.

Addressing: Foreign art collections including subject matter including data which specifies a location.

Clock or synchronization: Foreign art collections including subject matter including a reference timing function or a clock pulse generator for causing the various parts of the device to operate on a common time base.

Determination of marginal operation limits: Foreign art collections including subject matter in which the device or system is tested under controlled and varying circuit parameters, such as input voltage, to determine the range of circuit parameter values within which the device or system operates without error or malfunction.

DIGITAL DATA ERROR CORRECTION: Foreign art collections including subject matter in which the error in information content of pulse or pulse coded data is corrected.

Substitution of previous valid data: Foreign art collections including subject matter in which a previously validated data state or value is substituted for data state or value determined to be erroneous.

Request for retransmission: Foreign art collections including subject matter in which the digital data error correction is achieved by retransmission of data responsive to a request.

Retransmission if no ACK returned: Foreign art collections including subject matter in which a retransmission of data is initiated upon the condition that no acknowledgement (ACK) signal is returned from the receiver.

Feedback to transmitter for comparison: Foreign art collections including subject matter in which the digital data is returned to the transmitter for comparison to detect an error.

Including forward error correcting capability: Foreign art collections including subject matter in which the digital data is encoded to enable error correction at the receiver and retransmission is requested only if the error rate exceeds the forward error correcting capability.

Forward correction by block code: Foreign art collections including subject matter in which a grouping of symbols (i.e.., a block of data or a data word) is transformed into a code word having an increased number of symbols in order to provide an increased minimum distance between code words relative to the minimum distance of the corresponding data words in order to provide for forward correction of the encoded data in the event that an error or erasure is subsequently imposed on the encoded data.

Double error correcting with single error correcting code: Foreign art collections including subject matter in which a single bit error correcting code arrangement corrects double bit errors by successively correcting consecutive single bit errors.

Error correction during refresh cycle: Foreign art collections including subject matter including a digital data storage device having a refresh cycle in which decaying information is read before it becomes unrecognizable, and rewritten in original form, and decoding a stored block data code signal for error correction during the refresh cycle.

Double encoding codes (e.g., product, concatenated): Foreign art collections including subject matter including calculation and independent decoding of two independent sets of check words for enhancement of error correction.

Cross-interleave reed-solomon code (CIRC): Foreign art
collections including subject matter doubly encoded with Reed-Solomon codes and interleaved to enable the correction of burst errors.

Parallel generation of check bits: Foreign art collections including subject matter having plural check bit calculating elements connected in parallel.

Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity): Foreign art collections including subject matter which encodes digital data with both an error correcting code (ECC) for error correction and detection, and an additional error detection code to detect uncorrected errors.

Look-up table encoding or decoding: Foreign art collections including subject matter having an encoder or decoder which contains a table of all possible error patterns in a corrupted received code word and compares the computed syndrome to these patterns to determine the position of erroneous bits.

Threshold decoding (e.g., majority logic): Foreign art collections including subject matter the decoder operates upon a corrupted received code word to compute the parity check sums which are applied to a threshold or majority gate and an error indicated if the sums exceed a certain value.

Random and burst error correction: Foreign art collections including subject matter in which the block code is capable of correcting both random and burst errors.

Burst error correction: Foreign art collections including
subject matter in which the block code is derived to be most effective in correcting burst errors.

Memory access: Foreign art collections including subject matter in which digital data being written into or read out of a storage device is encoded in a block code format.

Error correct and restore: Foreign art collections including subject matter which corrects the errors upon readout of the data and the corrected data in written into memory as a substitute for the erroneous data.

Error pointer: Foreign art collections including subject matter which generates a signal (pointer) upon the occurrence of a particular type of error or failure.

Check bits stored in separate area of memory: Foreign art collections including subject matter including a section of memory for storage of the check bits separate from that the section of memory storing data information.

Code word for plural n-bit (n>1) storage units (e.g., x4 DRAM's): Foreign art collections including subject matter in which there is more than one storage device, each storing more than a single digit of data.

Error correction code for memory address: Foreign art collections including subject matter where the block code includes a memory address as part of the encoded data.

Dynamic data storage: Foreign art collections including subject matter where there is relative motion between a transducer and an information storage medium.

Disk array: Foreign art collections including subject matter where the storage medium is a plurality of interconnected disks.

Tape: Foreign art collections including subject matter where the storage medium is essentially of a two dimensional shape with one dimension being very long in relation to the other.

Code word parallel access: Foreign art collections including subject matter in which the bits of the code word are created from parallel data digits.

Solid state memory: Foreign art collections including subject matter where the storage device is or contains a solid state device (e.g., an integrated circuit or transistor).

Adaptive error-correction capability: Foreign art collections including subject matter in which the error-correction capability of the system is adapted to the existing error rate by selection of encoding format.

Synchronization: Foreign art collections including subject matter in which a lack of synchronization between encoder and decoder is detected and/or corrected.

For packet or frame multiplexed data: Foreign art collections including subject matter where plural encoded data streams are simultaneously transmitted over a common transmission medium in such a manner that the information signals may be discretely recovered, wherein each data stream contains one or more bytes preceded by an address header or where the simultaneously transmitted plurality of data streams include synchronization or other control information.

Hamming code: Foreign art collections including subject matter where there are m information code elements and k error check code elements such that there are sufficient check elements to correct a single error and the k check elements are determined by even parity checks in conjunction with element values appearing in certain selected information positions where each of the elements of the code group must be in a parity check subgroup with one or more of the check elements and no two different code elements having exactly the same set of check elements associated with it.

Nonbinary data (e.g., ternary): Foreign art collections including subject matter where each bit of a data word can assume more than two values.

Variable length data: Foreign art collections including subject matter where the number of bits in a data word is not fixed, but can vary from word to word.

Using symbol reliability information (e.g., soft decision): Foreign art collections including subject matter where, during error correction, in addition to an error correcting code, use is made of information about the reliability of the decoding of a particular bit.

Code based on generator polynomial: Foreign art collections including subject matter where a code word c(x), where x is a
unit delay operator, is generated by dividing a delayed version of the data polynomial d(x), i.e.,. xnd(x), by a generator polynomial, g(x), and subtracting the remainder from the delayed version of the data polynomial, thereby producing a code word that is a multiple of the generator polynomial, and where the data polynomial d(x) is such that positions within the block correspond to powers of x and data values at the positions correspond to polynomial coefficient values.

Bose-Chaudhuri-Hocquenghem code: Foreign art collections including subject matter where the block code is a t error correcting code which is the set of all polynomials {a(c)} over the Galois field GF(2m) of degree n-1 or less, such that a(ai)=0, for i=1,3,5,...,2t-1 where a is a primitive element of the finite field GF(2m), and where c is the radix 2 for binary data, a(c)=a0+a1c+a2c2+...+an-1cn-1, and aj=0,1 (j=0,1,2,..., n-1).

Golay code: Foreign art collections including subject matter where the block code is an (n, k, t) type polynomial code in which each code word is n=23 bits long, contains k=13 data or information bits, corrects up to t=3 errors, and the code word also contains (n-k)=10 redundant check bits.

Reed-Solomon code: Foreign art collections including subject matter where the block code consists of K data and N-K check symbols, where N is an arbitrary number and K is less than N, and where each symbol is made of J binary bits encoded with a generator polynomial g(x) for the code and a field generating polynomial M(x) which defines the Galois field.

Syndrome computed: Foreign art collections including subject matter where decoded data is divided by an inverse of the generator polynomial to obtain a data word of 1 bit which indicate which bits of the decoded data are in error.

Forward error correction by tree code (e.g., convolutional): Foreign art collections including subject matter in which information bits are encoded to generate a plurality of check bits, each check bit is generated as a function of a different plurality of information bits and is interspersed among the information bits at predetermined intervals with no natural beginning point or ending point (i.e.., there is no length restriction for the encoded data).

Random and burst errors: Foreign art collections including subject matter in which the convolutional code is capable of correcting both random and burst errors.

Burst errors: Foreign art collections including subject matter in which the convolutional code corrects for burst errors.

Synchronization: Foreign art collections including subject matter in which a lack of synchronization between the encoder and decoder is detected and/or corrected.

Puncturing: Foreign art collections including subject matter where single bits are periodically deleted at intervals from a low-rate convolutional code.

Sequential decoder (e.g., Fano or stack algorithm): Foreign art collections including subject matter where a tree structure of the convolutional code is used for searching locally a path which is considered to be the most likely to produce a correct data sequence.

Trellis code: Foreign art collections including subject matter where, for a convolutional code of k bits length, an
inverse coding operation is performed in which 2k-1 decision bits are used to select an output bit and where after many branches, the most probable path will be selected with a high degree of certainty, and where the branches form a mesh pattern (i.e.., branches start at a plurality of points and intersect other branches).

Syndrome decodable (e.g., self orthogonal): Foreign art collections including subject matter where decoded data is divided by an inverse of the generator polynomial to obtain a data word of 1 bit which indicate which bits of the decoded data are in error.

Maximum likelihood: Foreign art collections including subject matter where a decoder selects the sequence out of all the possible transmitted sequences which is most likely to match the received data sequence and determines corresponding digital (data) information.

Viterbi decoding: Foreign art collections including subject matter where data is not decoded as soon as it is received, instead, a sequence of data, having a predetermined decoding depth, following the digit to be decoded is first collected, then, by computing what are known as path metrics, a limited number of possible messages are selected, each extending throughout the decoding depth far beyond the digit presently to be decoded, with one such survivor sequence ending in each of the data states.

Branch metric calculation: Foreign art collections including subject matter where a tree of possible data sequences is constructed identifying the possible data sequences in terms of data states, and from which correlations are computed for selecting the paths which are to survive to the next stage of decoding received data.

Majority decision/voter circuit: Foreign art collections
including subject matter in which error correction is effectively achieved by error masking (making error invisible at output) through majority logic or voting techniques.

ERROR DETECTION FOR SYNCHRONIZATION CONTROL: Foreign art collections including subject matter in which error detecting techniques are utilized to detect an out-of-synch condition or to control synchronization between devices.

ERROR/FAULT DETECTION TECHNIQUES: Foreign art collections including subject matter in which specific techniques are recited for detecting an error or fault condition.

Parity bit: Foreign art collections including subject matter in which a redundant bit is added to a block of data bits.

Parity generator or checker circuit detail: Foreign art collections including subject matter which specify the particular elements of a parity signal source or comparitor circuit.

Even and odd parity: Foreign art collections including subject matter wherein the parity scheme in the system includes the generation of parity bits on both an even and odd basis.

Parity prediction: Foreign art collections including subject matter which calculates an expected parity value prior to execution of an operation and is subsequently compared to the actual parity value to detect an error.

Plural dimension parity check: Foreign art collections including subject matter in which a single parity bit is derived from data bits taken over each of two or more dimensions, such as horizontal and vertical parity.

Storage accessing (e.g., address parity check): Foreign art collections including subject matter in which the parity bit is calculated for data bits read into or read out of an information signal storage device.

Constant-ratio code (m/n): Foreign art collections including subject matter in which a code constraint of a constant-ratio between bits of a first logic state and a second logic state is utilized to enable error/fault detection.

Check character: Foreign art collections including subject matter in which a check character, derived as a predetermined function of a group of data bits, is associated with the group of data bits for error detection purposes.

Modulo-n residue check character: Foreign art collections including subject matter in which a check character, calculated as the remainder after the value of the digital data is divided by the modulus-n, is associated with the digital data to enable error/fault detection.

Code constraint monitored: Foreign art collections including subject matter in which the digital data encoding scheme provides inherent constrained conditions which are monitored to enable error/fault detection.

Multilevel coding (n 2): Foreign art collections including subject matter in which the digital data is encoded in a multilevel or multistate format where the number of levels or states in greater than 2.

Forbidden combination or improper condition: Foreign art collections including subject matter in which a forbidden combination of digital data or improper condition of a device is monitored to enable error or fault detection.

Specified digital signal pattern or pulse count: Foreign art collections including subject matter in which the forbidden combination is either a specified pattern of digital data or a count of one or more types of digital pulses.

Two key-down detector: Foreign art collections including subject matter in which the improper condition is the simultaneous activation of two or more keys on a data input device.

Data timing/clocking: Foreign art collections including subject matter in which the timing or clocking of digital data is monitored to detect a predetermined forbidden combination or condition.

Time delay/interval monitored: Foreign art collections including subject matter in which the time delay between events or data is detected to determine a predetermined forbidden condition.

Two-rail logic: Foreign art collections including subject matter in which both the true and complement state of each logic function is provided and the simultaneous occurrence of
both states indicates a forbidden combination.

Noise level: Foreign art collections including subject matter in which the forbidden condition is the presence of noise exceeding a predetermined level.

Missing-bit/drop-out detection: Foreign art collections including subject matter in which the improper combination is a missing bit or dropout of a bit within a data character.

Comparison of data: Foreign art collections including subject matter in which an error or fault is detected by the comparison of data.

Plural parallel devices or channel: Foreign art collections including subject matter in which the data from plural parallel devices or channels is compared to detect an error or fault.

Transmission facility: Foreign art collections including subject matter which detects an error or fault in a device including a channel of a transmission medium with a device for supplying a digital signal thereto.

Sequential repetition: Foreign art collections including subject matter in which an error or fault is detected by comparison of repetitive data.

True and complement data: Foreign art collections including
subject matter in which the data being transferred and compared comprises both the true and complement bit states of the data.

Device output compared to input: Foreign art collections including subject matter in which the error/fault detection is enabled by comparing the device output with the device input.

MISCELLANEOUS: Foreign art collections including subject matter not hereinabove classified.

RELIABILITY AND AVAILABILITY: Foreign art collections including subject matter further including means or steps for increasing a conditional probability of correctly performing services (e.g., data processing) throughout a time interval, given correct performance at the beginning of the interval, or for increasing the probability of correctly performing services at any given instant.

Fault recovery: Foreign art collections including subject matter further including means or steps for responding to a failure by either returning a system to a previous level of correct operation, achieving a degraded level of correct operation, or safely shutting down the system after detecting the error or locating the fault.

By masking or reconfiguration: Foreign art collections including subject matter further including means or steps for recovery by selecting a correct output from a concurrently active redundant functional unit in place of the output of the failed functional unit, or by replacing or isolating the failed functional unit.

Of network: Foreign art collections including subject matter further including means or steps for recovery at a network level (e.g., recovery from nodal failures).

Of memory or peripheral subsystem: Foreign art collections including subject matter further including means or steps for recovery from a fault of a memory function level or the peripheral function level, or for recovery limited to a specialized processor accessing either memory, peripheral, or other I/O device.

Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data): Foreign art collections including subject matter further including means or steps for recovery by accessing redundant stored data.

With reconfiguration (e.g., adding a replacement storage component): Foreign art collections including subject matter further including means or steps for statically replacing a failed memory component.

Isolating failed storage location (e.g., sector remapping): Foreign art collections including subject matter further including means or steps for recovery by disabling access to a failed memory location.

Access processor affected (e.g., I/O processor, MMU, DMA processor): Foreign art collections including subject matter further including means or steps for recovery from fault of an access processor (e.g., memory management unit (MMU), direct memory access (DMA) processor, I/O processor, etc.).

Of processor: Foreign art collections including subject matter further including means or steps for recovery from fault of a processor.

Concurrent, redundantly operating processors: Foreign art collections including subject matter further including means or steps for recovery employing redundant processors substantially simultaneously performing the same operation.

Synchronization maintenance of processors: Foreign art collections including subject matter further including means or steps for maintaining processor state synchronization to achieve redundancy of operation.

Prepared backup processor (e.g., initializing cold backup) or updating backup processor (e.g., by checkpoint message): Foreign art collections including subject matter further including means or steps for readying a backup processor or digital data processing system to replace a failed primary processor or digital data processing system, or to receive recent processing result(s) from a backup processor or digital data processing system that may be relied upon.

Of power supply: Foreign art collections including subject matter further including means or steps for recovery using power supply subsystem component redundancy.

State recovery (i.e., process or data file): Foreign art collections including subject matter further including means or steps for recovery by restoring data in a data file, or data for a process, to data at a previous point in time.

With forward recovery (e.g., redoing committed action): Foreign art collections including subject matter further including means or steps for recovery by reexecuting an operation in response to detecting an error in an operation.

Reexecuting single instruction or bus cycle: Foreign art collections including subject matter further including means or steps for recovery by retrying single instruction or bus cycle.

Transmission data record (e.g., for retransmission): Foreign art collections including subject matter further including means or steps for recovery of a communication process (e.g., a session) using a record.

Undo records: Foreign art collections including subject matter further including means or steps for recovery of data in the presence of uncommitted action using a record of the data created before the action.

Plural recovery data sets containing set interrelation data (e.g., time values or log record numbers): Foreign art collections including subject matter further including means or steps for recovery using sets of sequenced or linked recovery data containing set sequencing or linking data.

With state validity check: Foreign art collections including subject matter further including means or steps wherein recovery is controlled by verifying the accuracy of the state data.

With power supply status monitoring: Foreign art collections including subject matter further including means or steps
wherein recovery is controlled by a power supply status monitor.

Resetting processor: Foreign art collections including subject matter further including means or steps for recovery using clearing or initializing of a processor register.

Safe shutdown: Foreign art collections including subject matter further including means or steps for recovery including termination of a system component to a safe condition.

Fault locating (i.e., diagnosis or testing): Foreign art collections including subject matter further including means or steps for pinpointing a fault using either a reactive diagnosing or a proactive testing, including testing for developmental stage fault avoidance, for assurance, or for maintenance.

Artificial intelligence (e.g., diagnostic expert system): Foreign art collections including subject matter wherein the testing is performed using an artificial intelligence technique; e.g., fault tree, reasoning rules, self-learning.

With particular access structure: Foreign art collections including subject matter further including means or steps related to an access structure specialized for observing or controlling a test or diagnosis.

Substituted emulative component (e.g., emulator microprocessor): Foreign art collections including subject matter further including means or steps for using a tester component that can emulate (i.e., functionally operate as) a
normal component in the tested system.

Memory emulator feature: Foreign art collections including subject matter further including means or steps for using memory that can functionally replace a system component.

Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path): Foreign art collections including subject matter further including means or steps for testing or diagnostic access using specialized testing or diagnosing hardware permanently built into a component of the system being tested or diagnosed.

Additional processor for in-system fault locating (e.g., distributed diagnosis program): Foreign art collections including subject matter further including an additional processor for controlling all or part of in-system testing or diagnosis.

With particular stimulus creation: Foreign art collections including subject matter further including means or steps for selection or generation of a signal (i.e., data) for testing or diagnosing.

Derived from analysis (e.g., of a specification or by simulation): Foreign art collections including subject matter further including means or steps for deriving a test or diagnosis program based on an analysis of specification, design, or output of the system to be tested or diagnosed.

Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping): Foreign art collections
including subject matter further including means or steps for controlling a processor or digital data processing system to be tested or diagnosed by applying an interrupt, halt, or clock signal to a processor or digital data processing system.

Substituted or added instruction (e.g., code instrumenting, breakpoint instruction): Foreign art collections including subject matter further including means or steps for substituting or adding a testing or diagnosing instruction into a program or instruction data stream of a processor or digital data processing system being tested or diagnosed.

Test sequence at power-up or initialization: Foreign art collections including subject matter further including means or steps for performing a sequence of tests automatically in response to a power-up or initialization action.

Analysis (e.g., of output, state, or design): Foreign art collections including subject matter further including means or steps for evaluating the output, state, or design, of a computer system or a processor or a program, for fault locating.

Of computer software: Foreign art collections including subject matter further including means or steps for locating a fault in software or testing software.

Monitor recognizes sequence of events (e.g., protocol or logic state analyzer): Foreign art collections including subject matter further including means or steps for locating a fault by using a monitor for classifying or otherwise recognizing a sequence of events.

Component dependent technique: Foreign art collections including subject matter further including means or steps for fault locating that are specific to a device under test.

For reliability enhancing component (e.g., testing backup spare, or fault injection): Foreign art collections including subject matter further including means or steps for fault locating specific to fault in a reliability enhancing component.

Memory or storage device component fault: Foreign art collections including subject matter further including means or steps for fault locating specific to a fault in a memory.

Bus, I/O channel, or network path component fault: Foreign art collections including subject matter further including means or steps for fault locating specific to a fault in a bus, peripheral or I/O channel, or network path.

Peripheral device component fault: Foreign art collections including subject matter further including means or steps for fault locating specific to a fault in a peripheral device.

Output recording (e.g., signature or trace): Foreign art collections including subject matter further including means or steps for recording output from the system under test or diagnosis.

Operator interface for diagnosing or testing: Foreign art collections including subject matter further including means or steps for interfacing with an operator for fault locating.

Performance monitoring for fault avoidance: Foreign art collections including subject matter further including means or steps for monitoring event durations and event counts for anticipating or recognizing faults.

Error detection or notification: Foreign art collections including subject matter further including means or steps for automated on-line sensing of errors, or for storing or propagating such error information (e.g., error logging).

State error (i.e., content of instruction, data, or message): Foreign art collections including subject matter further including means or steps for detecting an error based on the information content of an instruction, a message, or data.

State out of sequence: Foreign art collections including subject matter wherein an ordering of state information related to a succession of data, instructions etc., is the basis for state analysis.

Control flow state sequence monitored (e.g., watchdog processor for control-flow checking): Foreign art collections including subject matter to detect state errors in an instruction data sequence.

Error checking code: Foreign art collections including subject matter for detecting consistency of information by using a code (e.g., parity, etc.) which is generated from the information.

Address error: Foreign art collections including subject matter further including means or steps for detection or notification of error of address state.

Storage content error: Foreign art collections including subject matter further including means or steps for detection or notification of error of storage state.

Timing error (e.g., watchdog timer time-out): Foreign art collections including subject matter further including means or steps for detection or notification of error of timing.

Bus or I/O channel device fault: Foreign art collections including subject matter further including means or steps for detecting errors related to a flaw in a bus, peripheral, or I/O channel device.

Error forwarding and presentation (e.g., operator console, error display): Foreign art collections including subject matter further including means or steps for propagating error information so as to make notification of detected error.