U.S. PATENT AND TRADEMARK OFFICE
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U.S. Patent Classification System - Classification Definitions
as of June 30, 2000
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Class 711
ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS:
MEMORY
Class Definition:
This class provides, within an electrical computer or digital
data processing system, for the following subject matter:
A. Processes and apparatus for addressing memory wherein the
processes and apparatus involve significant address
manipulating (e.g., combining, translating, or mapping and
other techniques for formatting and modifying address data)
and are combined with specific memory configurations or
memory systems;
B. Processes and apparatus for accessing and controlling
memory (e.g., transferring and modifying address data,
selecting storage devices, scheduling access); and
C. Processes and apparatus for forming memory addresses
(e.g., virtual memory addressing, address translating,
translation-lookaside buffers (TLBs), boundary checking, and
page mode).
SCOPE OF THE CLASS
(1) Note. In the instance where a peripheral is a memory,
classification herein is proper.
(2) Note. Classification herein requires more than nominal
recitation of addressing techniques or of memory accessing or
controlling in combination with digital data processing
systems or data processing. A nominal combination refers to a
combination wherein one or more of the means or steps thereof
are recited so broadly, and without details, as to constitute
a mere identification rather than a description of each means
or step.
(3) Note. Memory devices, per se, are classified in their
respective device classes. More specifically, registers and
data bearing records (e.g., smart cards) are classified
elsewhere. Static memory devices including internal elements
of memories are classified elsewhere. Display memory
organizations and structures (i.e., selective visual display
systems) such as memories defined by graphics processing
systems and graphics processing that involves interfacing
with memory are classified elsewhere. Devices (e.g.,
printers) that include memory for processing data for static
presentation (i.e., for viewing on a fixed medium such as
paper) are classified elsewhere. Dynamic magnetic information
storage or retrieval devices (e.g., magnetic disks, tapes,
drums, etc.) are classified elsewhere. Dynamic information
storage or retrieval devices (e.g., optical disks, CD-ROMs,
jukebox mechanics, and other storage devices having magnetic
and mechanical components) are classified elsewhere. See the
SEARCH CLASS notes below.
(4) Note. Processes and apparatus for transferring data
between memories of different computers directly (i.e., with
minimum or no intervention from main processors of the
computers) are classified elsewhere. See the SEARCH CLASS
notes below.
(5) Note. Processes and apparatus for direct memory access
(DMA) (i.e., the transferring of data between peripherals and
memories of a computer or digital data processing system with
minimal or no intervention from the main processor of the
computer or digital data processing system) are classified
elsewhere. See the SEARCH CLASS notes below.
(6) Note. Processes and apparatus for accessing and
retrieving instruction data of a fixed or variable length
from a memory or buffer and for shifting such instruction
data to align it with a physical memory or buffer boundary
are classified elsewhere. See the SEARCH CLASS notes below.
REFERENCES TO OTHER CLASSES
SEE OR SEARCH CLASS:
235, Registers, various subclasses for basic machines and
associated indicating mechanisms for ascertaining the number
of movements of various devices and machines; machines made
from these basic machines alone (e.g., cash registers, voting
machines) and in combination with various perfecting features
such as printers and recording means; and various systems
controlled by data bearing records (e.g., smart cards).
257, Active Solid-State Devices (e.g., Transistors,
Solid-State Diodes), subclass 202 for repeating geometric
arrangement of individual structural elements of solid-state
devices, and subclasses 368 and 390 for matrix or array of
field effect transistors (FETs).
326, Electronic Digital Logic Circuitry, 37 for
multifunctional or programmable logic (e.g., gate arrays) and
subclasses 52+ and 104+ for generic logic functions such as
EXOR, AND, OR, NOT and decoding in general.
340, Communications: Electrical, 825 for controlling one or
more devices to obtain a plurality of results by transmission
of a designated one of plural distinctive control signals
over a smaller number of communication lines or channels,
particularly subclass 825.02 for tree or cascade selective
communication, subclasses 825.03+ for channel selection,
subclasses 825.06+ for communication systems where status of
a controlled device is communicated, subclasses 825.2+ for
synchronizing selective communication systems, subclasses
825.5+ for lockout or priority in selective communication
systems, subclasses 825.52+ for selective communication
addressing, subclasses 825.57+ for pulse responsive
actuation; and subclasses 825.79+ for selective matrix which
may be used for control or as a switching means.
341, Coded Data Generation or Conversion, various subclasses
for electrical pulse and digit code converters (e.g., systems
for originating or emitting a coded set of discrete signals
or translating one code into another code wherein the meaning
of the data remains the same but formats may differ).
345, Computer Graphics Processing, Operator Interface
Processing, and Selective Visual Display Systems, 1 for
visual display systems with selective electrical control
including display memory organization and structure for
storing image data and manipulating image data between a
display memory and display peripheral, subclasses 507+ for
memory organization and structure for storing images to be
displayed, and subclass 521 for s:graphic processing that
involves interfacing with memory.
353, Optics: Image Projectors, 25 for selective data
retrieval of stored information viewed by a projection
means.
360, Dynamic Magnetic Information Storage or Retrieval (which
is an integral part of Class 369 following subclass 18 ), for
record carriers and systems wherein data are stored and
retrieved by interaction with a medium and there is relative
motion between a medium and a transducer (e.g., magnetic disk
drives, tapes, and drums and control thereof, per se),
particularly subclasses 72.1+ for locating a specific area in
storage.
361, Electricity: Electrical Systems and Devices, 684 for
computer storage component combined with housing or mounting
arrangement having no data processing or calculating
procedures.
364, Data Processing: Generic Control Systems or Specific
Applications, appropriate subclasses and particularly
subclasses 1-89 for data processing generic control systems
and subclasses 90-306 for computer and data processing system
applications.
365, Static Information Storage and Retrieval, various
subclasses for static memory devices including internal
elements of the memory, particularly 189.01 for read/write
circuits and subclasses 230.01+ for addressing of
addressable, static single storage elements or plural
elements; subclass 189.05 for buffering or latching data
being read from or written to memory; subclass 189.08 for
logic devices in combination with memory systems; subclasses
200 and 201 for testing of memory systems; and subclass
230.08 for buffering and latching address data being employed
to access memory.
369, Dynamic Information Storage or Retrieval, various
subclasses for record carriers and systems wherein data are
stored and retrieved by interaction with a medium and there
is relative motion between a medium and a transducer (e.g.,
optical disks, CD-ROMs, jukeboxes), particularly 30, 69, and
176+ for designating or selecting storage media to be used
for storage and retrieval.
370, Multiplex Communications, appropriate subclasses for
multiplex switching techniques similar to addressing and the
handling of memory information signals and for the
simultaneous transmission of two or more signals over a
common medium, particularly 351 for time division multiplex
(TDM) switching, subclasses 475+ for asynchronous TDM
communications including addressing, and subclasses 498+ for
time division bus transmission.
377, Electrical Pulse Counters, Pulse Dividers, or Shift
Registers: Circuits and Systems, 64 for shift registers.
380, Cryptography, 3 for stored data access or copy
prevention (e.g., software program protection or computer
virus detection) in combination with data encryption, and
subclasses 49+ for digital signal handling with shift
register or memory.
395, Information Processing System Organization, appropriate
subclasses and particularly subclass 1, 3 through 77, 900,
and 902 through 934 for artificial intelligence type
computers and digital data processing systems; subclasses
115+ for process and apparatus (e.g., printer) that includes
memory for processing data for static presentation (i.e., for
viewing on a fixed medium such as paper); subclasses 200.3+
for transferring data between a plurality of computers,
particularly subclass 200.42 for computer-to-computer direct
memory accessing and subclasses 200.43+, wherein the
transferring is via a shared memory.
701, Data Processing: Vehicles, Navigation, and Relative
Location, appropriate subclasses for applications of
computers in vehicular and navigational environments.
702, Data Processing: Measuring, Calibrating, or Testing,
subclass 80 for specified memory location generation for
storage of an electrical signal parameter measurement.
704, Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression, 1
for applications of computers in linguistics, subclasses 200+
for applications of computers in speech signal processing,
and subclasses 500 through 504 for applications of computers
in audio compression/decompression.
705, Data Processing: Financial, Business Practice,
Management, or Cost/Price Determination, appropriate
subclasses for applications of computers and calculators in
business and management environments.
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 1, 100+, and 200+ for
data retrieval, file or database management, garbage
collection, file configuration and initialization, and
allocation.
708, Electrical Computers: Arithmetic Processing and
Calculating, 1 for electric hybrid computers; subclasses
100+ for electric digital calculating computers; and
subclasses 800+ for electric analog computers.
710, Electrical Computers And Digital Data Processing
Systems: Input/Output, 1 for transferring data from one or
more peripherals to one or more computers for the latter to
process, store, or further transfer or for transferring data
from the computers to the peripherals, particularly
subclasses 22+ for direct memory access (DMA) (i.e., the
transferring of data between peripherals and memories of a
computer or digital data processing system with minimal or no
intervention from the main processor of the computer or
digital data processing system).
712, Electrical Computers And Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), 1 for processing architectures such as MIMD,
vector, or array processors; subclass 204 for instruction
alignment; subclasses 205+ for instruction fetching;and
subclasses 200 through 248 for various instruction processing
not involving I/O such as executing.
713, Electrical Computers and Digital Processing Systems:
Support, 200 for furthering the security of computers,
digital data processing systems and peripherals.
714, Error Detection/Correction and Fault Detection/Recovery,
various subclasses for detecting or correcting errors in
generic electrical pulse or pulse coded data and for
detecting and recovering from faults of computers, digital
data processing systems, and logic level based systems,
particularly subclass 702 for memory access (e.g., address
permutation); subclasses 710+ for replacement with spare
memory components or portion thereof; subclasses 718+ for
memory testing; and subclasses 763+ for memory access with
error correction, error pointer, or error checking.
901, Robots, appropriate cross-reference art collections for
reprogrammable, multifunction manipulators designed to move
devices.
GLOSSARY:
The terms below have been defined for purposes of
classification in this class and are shown in underlined type
when used in the class and subclass definitions. When these
terms are not underlined in the definitions, the meaning is
not restricted to the glossary definitions below.
ADDRESS DATA
Data that specify a location in a memory.
BUS
A conductor used for transferring data, signals, or power.
COMPUTER
A machine that inputs data, processes data, stores data, and
outputs data.
DATA
Representation of information in a coded manner suitable for
communication, interpretation, or processing. See ADDRESS
DATA, INSTRUCTION DATA, STATUS DATA, and USER DATA in this
glossary,
DATA PROCESSING
See PROCESSING below.
DIGITAL DATA PROCESSING SYSTEM
An arrangement of processor(s) in combination with either
memory or peripherals, or both, performing data processing.
INFORMATION
Meaning that a human being assigns to data by means of the
conventions applied to that data.
INSTRUCTION DATA
Data that represent an operation and identify its operands,
if any.
MEMORY
A functional unit to which data can be stored and from which
data can be retrieved.
PERIPHERAL
A functional unit that transmits data to or receives data
from a computer to which it is coupled (e.g., modems,
keyboards, monitors, touch tablet, printers, joy stick, disk
and tape drives, etc.).
PROCESSING
Methods or apparatus performing systematic operations upon
data or information exemplified by functions such as data or
information transferring, merging, sorting, and calculating
(i.e., arithmetic operations or logical operations).
Note: In an effort to avoid redundant constructions, in this
class, where appropriate, the term address data processing is
used in place of address data data processing.
PROCESSOR
A functional unit that interprets and executes instruction
data.
STATUS DATA
Data that represent conditions of data, computers,
peripherals, memory, etc.
USER DATA
Data other than address data, instruction data, or status
data.
SUBCLASSES
Subclass:
1
ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR
SYSTEM:
This subclass is indented under the class definition.
Subject matter comprising means or steps for determining one
or more values (i.e., address data) that specify one or more
locations in a storage medium wherein the means or steps are
claimed in combination with a particular configuration or
system for storing data.
(1) Note. Classification herein requires significant address
manipulating (i.e., more than nominal recitation of an
addressing technique). Significant address manipulating is
exemplified by address data processing functions such as
combining, translating, mapping, and other techniques
associated with forming or modifying address data.
(2) Note. Means or steps for determining a value that
specifies a memory location (i.e., address data) must include
more than nominal recitation of processing functions and
memory components for classification herein.
(3) Note. This subclass and those indented below provide
for combinations of data processing, particular memory
systems, and significant address data manipulating.
Generalized addressing in a digital data processing system is
classified elsewhere in this class. See the SEARCH THIS
CLASS, SUBCLASS notes below.
(4) Note. This subclass and those indented below may
include means (e.g., processor, controller, etc.) or steps
for control of a memory of a digital data processing system
in combination with memory accessing (e.g., reading,
writing). Memory accessing and control for specific memory
compositions, hierarchical memory configurations, and shared
memory, however, is classified elsewhere. See the SEARCH THIS
CLASS, SUBCLASS notes below.
(5) Note. Means or steps for accessing and controlling
plural memory configurations (e.g., data farms, "library"
systems) that include significant data processing are
classified herein. Control systems for delivering storage
media (e.g., delivery of robotics or automated tapes or
cartridges, selection and delivery of platters), however, are
properly classified elsewhere under automated control or
another appropriate subclass in the respective device,
robotics, and generic control classes. In instances involving
significant data processing and significant details of media
delivery systems, classification herein is proper.
SEE OR SEARCH THIS CLASS, SUBCLASS:
3 for cache memory addressing.
101 through 116, for storage accessing and control for
various memory compositions (e.g., ROM, RAM, CAM, dynamic,
detachable, bubble, etc.) with more than nominal data
processing.
117 through 146, for storage accessing and control for
hierarchical memory with nominal address forming.
147 through 154, for storage accessing and control for
shared memory with nominal address forming.
200 for generalized address forming in data processing
systems.
SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, 105 for digital
logic decoding circuits in general.
340, Communications: Electrical, 825.79 for selective matrix
which may be used for control or as a switching means.
345, Computer Graphics Processing, Operator Interface
Processing, and Selective Visual Display Systems, 507 for
processing indices to locations (or addresses) of stored data
elements in a computer s:graphic processing system.
365, Static Information Storage and Retrieval, 189.01 for
read/write circuits, and subclasses 230.01+ for addressing of
addressable, static single storage elements or plural
elements of the same type.
369, Dynamic Information Storage or Retrieval, 30, 69, and
176+, as appropriate, for subject matter related to
designation or selection of storage medium to be used for
storage and retrieval.
370, Multiplex Communications, appropriate subclasses for
multiplex switching techniques similar to addressing or the
handling of memory information signals.
704, Data Processing: Speech Signal Processing, Linguistics,
Language Translation and Audio Compression/Decompression, 2
for memory control scheme combined with linguistics.
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 1 for database
management and file management systems including significant
addressing, retrieval, or manipulation of information
contained within a database of a digital data processing
system or computer including searching, query processing,
information locating and retrieval techniques from a file or
database; subclasses 100+ for database schema types; and
subclasses 200+ for file maintenance operations, allocating
or deallocating memory space to files, garbage collection,
and hierarchical or tree filling systems.
710, Electrical Computers And Digital Data Processing
Systems: Input/Output, 3 for Input/Output addressing,
subclass 9 for address assignment for configuring
peripherals, subclasses 22+ for direct memory accessing (DMA)
and subclasses 131+ for system intraconnecting switching.
901, Robots, appropriate cross-reference art collections for
reprogrammable, multifunction manipulators designed to move
devices.
Subclass:
2
Addressing extended or expanded memory:
This subclass is indented under subclass 1. Subject matter
wherein addresses are determined for memory not normally
accessible by a base operating system, computer, or digital
data processing system components.
(1) Note. Classification here may include virtual
addressing techniques; however, virtual memory addressing art
which deals with logical addressing techniques as opposed to
addressing for physical enhancements, such as extended and
expanded memory, is classified elsewhere in this class.
SEE OR SEARCH THIS CLASS, SUBCLASS:
203 for virtual addressing, per se.
Subclass:
3
Addressing cache memories:
This subclass is indented under subclass 1. Subject matter
wherein addresses are generated for memory nearest a
processor in a hierarchical memory arrangement (i.e., a cache
memory arrangement).
(1) Note. This subclass accommodates particular addressing
techniques for cache memory systems. Cache memory accessing
and control (i.e., reading and writing) are classified
elsewhere in this class. See the SEARCH THIS CLASS, SUBCLASS
notes below.
SEE OR SEARCH THIS CLASS, SUBCLASS:
117 for hierarchical memory arrangement accessing and
control, including cache memory in subclasses 118 through
146.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, 49 for
internal aspects of associative memory.
Subclass:
4
Dynamic-type storage device (e.g., disk, tape, drum):
This subclass is indented under subclass 1. Subject matter
wherein address schemes are particular to a data storage
device requiring relative motion between a data holding
medium and a recording mechanism such as disk, tape, or drum
memory.
SEE OR SEARCH CLASS:
360, Dynamic Magnetic Information Storage or Retrieval, which
is an integral part of Class 369, following subclass 18, for
record carriers and systems wherein information is stored and
retrieved by interaction with a medium and there is relative
motion between a medium and a transducer (e.g., magnetic disk
drive devices and control thereof, per se). See Class 360,
subclass 72.2 for addressing and control of recording
mechanism to locate the selected area.
369, Dynamic Information Storage or Retrieval, various
subclasses for record carriers and systems wherein
information is stored and retrieved by interaction with a
medium and there is relative motion between a medium and a
transducer. Particularly, see subclasses 30-34 for
selective addressing of dynamic storage medium.
Subclass:
5
For multiple memory modules (e.g., banks, interleaved
memory):
This subclass is indented under subclass 1. Subject matter
wherein logical addresses are determined and mapped (e.g.,
interleaving) across different physical memory arranged in
blocks, banks, partitions, etc.
(1) Note. This subclass includes subject matter directed to
static column or static row handling in multiple physical
memory module addressing.
SEE OR SEARCH THIS CLASS, SUBCLASS:
127 for interleaved cache.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass
230.03 and 230.04 for subject matter including plural banks
or blocks and alternating between them.
Subclass:
6
Virtual machine memory addressing:
This subclass is indented under subclass 1. Subject matter
wherein addresses are determined in a memory system
accommodating addressing requirements for software emulation
of a target computer or digital data processing system on a
base computer or digital data processing system.
(1) Note. Classification here includes virtual addressing
techniques (that is, for example, processing logical to
physical (real, absolute) address translation entries.
Virtual memory addressing deals with logical addressing
techniques. Classificaiton here is proper if there is
significant virtual memory processing for systems
accomodating emulation of a tarte computer of digital data
processin system on a base computer or digital data
processing system. Logical addressing for physical
enhancements, such as extended and expanded memory, is
classified elsewhere in theis class.
SEE OR SEARCH THIS CLASS, SUBCLASS:
202- 210, for address mapping and virtual addressing, per
se.
SEE OR SEARCH CLASS:
395, Information Processing System Organization, appropriate
subclasses and particularly subclass 406 for managing
processing tasks for virtual machines and subclass 527 for
compatibility, emulation, and simulation of systems or system
components.
Subclass:
100
STORAGE ACCESSING AND CONTROL:
This subclass is indented under the class definition.
Subject matter comprising means (e.g., a processor, a
controller, etc.) or steps for governing memory in a computer
or digital data processing system or the passage (e.g.,
reading, writing) of data thereto.
(1) Note. The subject matter of this subclass and the
subclasses thereunder provides for details of how memory is
accessed and controlled. Classification herein requires more
than nominal recitation of accessing or controlling memory in
the context of digital data processing systems or data
processing. Examples of significant memory accessing and
control data processing include transferring and modifying
memory address data, selecting memory devices or memory
locations, and scheduling memory accesses.
(2) Note. Storage devices such as static memory devices,
holographic stores, disk drives (and the mechanical control
of disk drives, e.g., head positioning, substrate speed,
etc.), and optical stores, are classified, per se, in their
respective device classes.
(3) Note. Subject matter classified herein may include
nominal recitations of address data generation, manipulation,
and modification. Combinations of a particular memory
construct (e.g., cache) with accessing and control and
significant addressing as exemplified by data processing
functions such as combining, translating, mapping, and other
techniques associated with forming and modifying addresses,
however, are classified in superior subclasses directed to
such combinations. See the SEARCH THIS CLASS, SUBCLASS notes
below.
(4) Note. Classification herein requires more than nominal
recitation of means or steps for controlling memory.
(5) Note. This subclass and the subclasses thereunder also
provide for subject matter wherein static or dynamic storage
forms part of a digital data processing system.
(6) Note. Subject matter classified herein may include
nominal recitations of reliability and availability in
combination with memory accessing and control. The species of
reliability and availability related to data archiving,
backup, and device access limiting and security combined with
memory accessing and controlling is classified herein. Other
species of reliability and availability combined with memory
accessing and controlling are classified elsewhere. See the
SEARCH THIS CLASS, SUBCLASS notes below.
(7) Note. Memories known as display memory, display
buffers, frame buffers, VRAMs, etc., functioning in
combination to store image data for image processing are
properly classified elsewhere. Subject matter for interfacing
between a graphics processor and a memory is classified
elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes and
SEARCH CLASS notes below for the information handling
subclasses relevant to memories acting on display data.
(8) Note. Means or steps for accessing and controlling
plural memory configurations (e.g., data farms, "library"
systems, etc.) including significant data processing are
classified here. Details of control systems for medium
delivery such as robotics or automated tape, cartridge, and
platter selection and delivery, however, are properly
classified elsewhere under automated control or another
appropriate subclass in the respective device, robotics, and
generic control classes. In instances where there is
significant data processing and significant details of medium
delivery systems, classification should be based on the
hierarchy of classes and classified here.
(9) Note. This subclass is directed to generic memory
accessing and control. Database accessing and retrieval is
classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS
notes below.
SEE OR SEARCH THIS CLASS, SUBCLASS:
161 for reliability and availability combined with memory
accessing and control provided for in this array. See the
(6) Note for subclass 100 above.
SEE OR SEARCH CLASS:
340, Communications: Electrical, 825 for controlling one or
more devices to obtain a plurality of results by transmission
of a designated one of plural distinctive control signals
over a smaller number of communication lines or channels,
particularly subclass 825.02 for tree or cascade selective
communication, subclasses 825.03+ for channel selection,
subclasses 825.06+ for communication systems where status of
a controlled device is communicated, subclasses 825.2+ for
synchronizing selective communication systems, subclasses
825.5+ for lockout or priority in selective communication
systems, subclasses 825.52+ for addressing, and subclasses
825.57+ for pulse responsive actuation.
345, Computer Graphics Processing, Operator Interface
Processing, and Selective Visual Display Systems, 507 for
memory organization and structure for storing images to be
displayed, and subclass 521 for interfacing between a
graphics processor and a memory.
353, Optics: Image Projectors, 25 for selective data
retrieval of stored information viewed by a projection
means.
361, Electricity: Electrical Systems and Devices, 684 for
computer storage component combined with housing or mounting
arrangement having no data processing or calculating
procedures.
369, Dynamic Information Storage or Retrieval, 30, 69, and
176+, as appropriate, for subject matter related to
designation or selection of storage medium to be used for
storage and retrieval.
370, Multiplex Communications, for the simultaneous
transmission of two or more signals over a common medium,
particularly 351 for time division multiplex (TDM)
switching, subclasses 475+ for asynchronous TDM
communications including addressing, and subclasses 498+ for
time division bus transmission.
395, Information Processing System Organization, 115 for
static presentation processing combined with memory; subclass
709 for software/program optimization of memory usage or
other resource usage (e.g., optimization by removing
redundancy, eliminating unnecessary memory accesses, etc.).
704, Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression, 2
for memory control scheme combined with linguistics.
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 1 for database
management and file management systems including significant
addressing, retrieval, or manipulation of information
contained within a database of a digital data processing
system or computer including searching, query processing,
information locating and retrieval techniques from a file or
database; subclasses 100+ for database schema types; and
subclasses 200+ for file maintenance operations, allocating
or deallocating memory space to files, garbage collection,
and hierarchical or tree filling systems.
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 1 for combinations of data transfers
performed by a peripheral (e.g., I/O processors, DMA, I/O
controllers, I/O adapters, etc.) between digital data
processing systems or computers and peripherals; subclasses
22+ for Direct Memory Access (DMA) or direct data transfers
to or from memory or to or from other peripherals and for
data transfers performed by a peripheral between external
components such as disk drives, peripheral devices, etc.,
which involves I/O processing; and subclasses 100+ for
connections within a single computer or digital data
processing system arrangement such as interfacing, bus
arbitration, bus expansion.
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), 220 for processing control and instruction
processing, per se, which often includes access to registers
surrounding functional units of a processor.
714, Error Detection/Correction and Fault Detection/Recovery,
1 for reliability and availability combined with memory
accessing and control not provided for herein (see the ( 6 )
Note above).
901, Robots, appropriate cross-reference art collections for
reprogrammable, multifunction manipulators designed to move
devices.
Subclass:
101
Specific memory composition:
This subclass is indented under subclass 100. Subject matter
wherein control of the memory or the accessing thereof is
adapted to the type of memory being accessed.
(1) Note. Structures and particulars of the memory device
itself are classified in the relevant device class.
(2) Note. Subject matter included herein is directed to the
specifics of accessing technique employed to access and
control the memory by computers, digital data processing
systems, processors, or other users.
(3) Note. The nature of data stored in a memory (i.e., the
information) does not make the memory "specific" within the
context of this and its indented subclasses (e.g., video or
image data, printer buffer, control data memory, etc.).
(4) Note. Accessing and controlling of a multiport memory,
per se, are classified elsewhere in this class. See the
SEARCH THIS CLASS, SUBCLASS notes below.
SEE OR SEARCH THIS CLASS, SUBCLASS:
131 for multiport cache.
149 for shared multiport memory.
SEE OR SEARCH CLASS:
235, Registers, 375 for systems controlled by data bearing
records.
313, Electric Lamp and Discharge Devices, 391 for cathode
ray tube storage devices.
326, Electronic Digital Logic Circuitry, 37 for
multifunctional or programmable logic (e.g., gate arrays) and
subclasses 52+ and 104+ for generic logic functions such as
EXOR, AND, OR, NOT, and decoding.
369, Dynamic Information Storage or Retrieval, 30, 69, and
176+, as appropriate, for subject matter related to
designation or selection of storage medium to be used for
storage and retrieval.
439, Electrical Connectors, 43 for plug board connections
and pins, and subclasses 55+ for preformed panel circuit
arrangements (e.g., ICs, chips, wafers, etc.).
902, Electronic Funds Transfer, cross-reference art
collections 25+ for smart card memories.
Subclass:
102
Solid-state read only memory (ROM):
This subclass is indented under subclass 101. Subject matter
including means or steps for accessing solid-state randomly
accessible nonvolatile memory (e.g., ROM).
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, appropriate
subclasses for storage having a particular internal cell
structure (e.g., subclass 94 for read only (i.e.,
semipermanent) systems), subclasses 189.01+ for memory
read/write circuits, and subclasses 230.01+ for addressing
circuits.
Subclass:
103
Programmable read only memory (PROM, EEPROM, etc.):
This subclass is indented under subclass 102. Subject matter
including means or steps for accessing and controlling
programmable solid-state nonvolatile memory (e.g., PROM,
EPROM, EEPROM, flash, etc.).
Subclass:
104
Solid-state random access memory (RAM):
This subclass is indented under subclass 101. Subject matter
including apparatus or method for accessing volatile randomly
accessible memory.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, 129 for
various memory elements used in random access memory
construction.
Subclass:
105
Dynamic random access memory:
This subclass is indented under subclass 104. Subject matter
including means or steps for accessing volatile memory
requiring periodic refreshing (e.g., DRAM, Dynamic RAM,
etc.).
Subclass:
106
Refresh scheduling:
This subclass is indented under subclass 105. Subject matter
including specifics of coordinating refreshing operations
with other system operations.
(1) Note. This subclass is proper for subject matter
directed to coordinating refresh scheduling with other system
events, accesses, requirements, etc., external to the memory
cells. However, coordinating the timing requirements within a
memory cell or composite thereof is classified elsewhere.
See the SEARCH CLASS notes below.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, appropriate
subclasses for timing requirements at the cell level and for
storage having a particular internal cell structure (e.g.,
subclass 222 for memory refreshing).
Subclass:
107
Ferrite core:
This subclass is indented under subclass 101. Subject matter
comprising arrays of magnetizable rings as the individual
storage elements.
(1) Note. In the 1960's the term "core memory" referred
exclusively to memory with ferrite cores. Also at that time,
the main memory of large systems were exclusively of this
type. As the art progressed, the term core memory became a
holdover to refer to the system's main memory, regardless of
the actual type of memory being used. Therefore, if core
memory is claimed, the specification should be checked to see
if the memory is indeed core memory (i.e., ferrite memory)
for classification here; otherwise, it should be treated as
solid-state memory and classified elsewhere.
SEE OR SEARCH THIS CLASS, SUBCLASS:
102 for ROM accessing and control.
104 for RAM accessing and control.
Subclass:
108
Content addressable memory (CAM):
This subclass is indented under subclass 101. Subject matter
including memory of the type where elements are addressed
according to the stored contents (e.g., associative memory,
etc.).
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass 49
and 50 for associative memories or content addressable
memories (CAM), per se.
Subclass:
109
Shift register memory:
This subclass is indented under subclass 101. Subject matter
including memory of the type where elements are arranged to
serially pass the stored contents from one location to an
adjacent location, or for use in data format conversion
within a digital data processing system.
(1) Note. Employing shift registers as part of the system
memory for transferring data within a digital data processing
system is classified here; however, the specifics of the
interconnections and control of shift register memories is
classified elsewhere. See the SEARCH CLASS notes below.
(2) Note. Although data format conversion may form part of
the overall combination in this subclass, data format
conversion, per se, is classified elsewhere. See the SEARCH
CLASS notes below.
SEE OR SEARCH CLASS:
235, Registers, 441, 492, and 493 for electrical records and
record sensors (i.e., IC cards).
341, Coded Data Generation or Conversion, appropriate
subclasses for digital to digital code converting.
377, Electrical Pulse Counters, Pulse Dividers, or Shift
Registers: Circuits and Systems, 64 for shift registers and
subclasses 107+ and 118+ for counters.
Subclass:
110
Circulating memory:
This subclass is indented under subclass 109. Subject matter
wherein the contents of a register may be passed in a
recirculating fashion among a group of adjacent registers
(e.g., ring buffers, barrel shifters, etc.).
Subclass:
111
Accessing dynamic storage device:
This subclass is indented under subclass 101. Subject matter
including accessing memory of the type where a storage medium
is moved relative to a transducer (e.g., magnetic or paper
tape, punched cards, etc.).
(1) Note. This and indented subclasses provide for dynamic
storage combined with significant digital data processing
system elements and functions.
SEE OR SEARCH CLASS:
235, Registers, 375 for various systems controlled by data
bearing records, subclasses 419+ for record controlled
calculators, and subclasses 435+ for coded record sensors.
360, Dynamic Magnetic Information Storage or Retrieval, 72.1
for locating a specific area in storage.
369, Dynamic Information Storage or Retrieval, various
subclasses for the arrangement of information within dynamic
storage alone.
Subclass:
112
Direct access storage device (DASD):
This subclass is indented under subclass 111. Subject matter
wherein devices employing a medium capable of being accessed
directly and by so doing skipping past portions of the
medium.
(1) Note. For purposes of this definition, memory devices
known typically as disks, drums, etc., are considered to be
of the direct access type whereas tapes are not.
Subclass:
113
Caching:
This subclass is indented under subclass 112. Subject matter
wherein the DASD is used as a dedicated hierarchically
intermediate store or with a dedicated hierarchically
intermediate store.
(1) Note. Caching in this subclass is (a) being performed
by a DASD device or (b) being supplied by another device in
combination with a DASD. Caching, per se, is classified
elsewhere.
SEE OR SEARCH THIS CLASS, SUBCLASS:
117 for hierarchical memory accessing and control and
caching, per se.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass 49
and 50 for associative memories and caches under their class
definition.
Subclass:
114
Arrayed (e.g., RAIDs):
This subclass is indented under subclass 112. Subject matter
where a plurality of direct access devices are arranged in an
array and files or portions thereof are stored on more than
one of the direct access storage devices.
(1) Note. This subclass is appropriate for redundant arrays
of inexpensive disks (RAID).
(2) Note. See the (6) Note to subclass 100 for systems
directed to reliability and availability of DASDs. See the
SEARCH CLASS notes below.
SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, 39 for programmable
gate arrays.
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 20 for systems directed to parallel
data transfer.
714, Error Detection/Correction and Fault Detection/Recovery,
5 for systems directed to reliability and availability of
DASDs.
Subclass:
115
Detachable memory:
This subclass is indented under subclass 101. Subject matter
wherein the memory is of the solid-state type and can be
readily physically connected and disconnected manually,
without the aid of any tools, for temporary or transient
purposes (e.g., replaceable memory cartridges, smart cards,
etc.).
SEE OR SEARCH THIS CLASS, SUBCLASS:
2 for addressing extended/expanded memory.
SEE OR SEARCH CLASS:
235, Registers, 441, 492, and 493 for electrical records and
record sensors (i.e., IC cards).
463, Amusement Devices: Games, subclass 44 for a cartridge
for game memory storage.
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 101 for bus expanding/extending and
hot card Inserting.
Subclass:
116
Bubble memory:
This subclass is indented under subclass 101. Subject matter
wherein the memory is of the solid-state type comprising one
or more series of persistent microscopically small magnetized
bubbles on a thin film substrate.
Subclass:
117
Hierarchical memories:
This subclass is indented under subclass 100. Subject matter
wherein the memory being accessed or controlled is in an
arrangement consisting of more than one ordered level of
memory.
Subclass:
118
Caching:
This subclass is indented under subclass 117. Subject matter
wherein portions of the data stored in slower main memory are
transferred to faster memory between processor(s) and the
main memory.
SEE OR SEARCH THIS CLASS, SUBCLASS:
113 for systems where a cache memory is created within a
DASD or dedicated to a DASD device.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass 49
and 50 for associative memories and caches at the cell
level.
Subclass:
119
Multiple caches:
This subclass is indented under subclass 118. Subject matter
employing plural cache memories arranged between at least one
processor and at least one main memory.
Subclass:
120
Parallel caches:
This subclass is indented under subclass 119. Subject matter
further comprising means or steps for employing plural cache
memories arranged at the same ordinal level between at least
one processor and at least one main memory.
Subclass:
121
Private caches:
This subclass is indented under subclass 119. Subject matter
further comprising means or steps for employing plural cache
memories where at least one of the caches is exclusively
associated with a respective one of a plurality of
processors.
Subclass:
122
Hierarchical caches:
This subclass is indented under subclass 119. Subject matter
further comprising means or steps for caching at a plurality
of different hierarchical levels (e.g., main cache coupled to
an on-chip cache).
Subclass:
123
User data cache and instruction data cache:
This subclass is indented under subclass 119. Subject matter
further comprising means or steps for employing separate or
partitioned cache(s) for separately storing portions of
instruction data and user data, respectively.
(1) Note. This physical separation of instruction data and
user data is often referred to as Harvard architecture in the
art and associated literature.
Subclass:
124
Cross-interrogating:
This subclass is indented under subclass 119. Subject matter
wherein an individual cache system must announce to other
cache systems or check with other cache systems which may
possibly contain a copy of a given cached location prior to
or upon modification or appropriation of data at a given
cached location.
Subclass:
125
Instruction data cache:
This subclass is indented under subclass 118. Subject matter
further comprising means or steps using a single cache
dedicated to caching instruction data.
SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), subclasses 200-219, 220+ and 300 for
instructional data processing, particularly 216+ for
instruction dependency checking and resolution.
Subclass:
126
User data cache:
This subclass is indented under subclass 118. Subject
further comprising means or steps for using a single cache
dedicated to caching user data.
Subclass:
127
Interleaved:
This subclass is indented under subclass 118. Subject matter
wherein consecutive cache memory locations are located in
different memory components.
SEE OR SEARCH THIS CLASS, SUBCLASS:
5 for interleaving in combination with multiple memory
modules with significant addressing.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass
230.03 and 230.04 for subject matter including plural banks
or blocks and alternating between them.
Subclass:
128
Associative:
This subclass is indented under subclass 118. Subject matter
further comprising organizing a cache system where any block
in main memory can be mapped to any block in the cache (fully
associative) or where the cache is divided into sets of
blocks and individual blocks of main memory are mapped to any
of the blocks of a particular corresponding set (that is, for
example, set associative).
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, 49 for
associative memories or content addressable memories (CAM),
per se.
Subclass:
129
Partitioned cache:
This subclass is indented under subclass 118. Subject matter
further comprising means or steps for dividing the cache into
independent sections or domains.
Subclass:
130
Shared cache:
This subclass is indented under subclass 118. Subject matter
further comprising means or steps for providing caching
functions to a plurality of processors from single cache.
Subclass:
131
Multiport cache:
This subclass is indented under subclass 118. Subject matter
further comprising caches composed of multiport memory
thereby allowing simultaneous reads from the cache by plural
processors.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass
230.05 for multiple port access devices.
Subclass:
132
Stack cache:
This subclass is indented under subclass 118. Subject matter
further comprising means or steps for caching stack data.
Subclass:
133
Entry replacement strategy:
This subclass is indented under subclass 118. Subject matter
including provisions for determining when the contents of a
cache location may be replaced with other data.
SEE OR SEARCH THIS CLASS, SUBCLASS:
203 for various generalized virtual addressing teachings.
Subclass:
134
Combined replacement modes:
This subclass is indented under subclass 133. Subject matter
using a combination that includes more than one entry
replacement determination mode.
Subclass:
135
Cache flushing:
This subclass is indented under subclass 133. Subject matter
including provisions to clear or reset the cache or
associated flags.
Subclass:
136
Least recently used:
This subclass is indented under subclass 133. Subject matter
where the determination is made based upon the time since the
last access to the contents of a given location.
Subclass:
137
Look-ahead:
This subclass is indented under subclass 118. Subject matter
where selected data from main memory are retrieved into the
cache prior to any request from the processor for the
selected data.
SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems:
Processing-Processing Architectures and Instruction
Processing (e.g., Processors) subclass 205 for fetching,
207 for prefetching, and 233+ for branch prediction.
Subclass:
138
Cache bypassing:
This subclass is indented under subclass 118. Subject matter
wherein selected memory accesses are not placed into or
retrieved from the cache.
Subclass:
139
No-cache flags:
This subclass is indented under subclass 138. Subject matter
including provisions for marking selected locations of main
memory so that the contents are not cached.
Subclass:
140
Cache pipelining:
This subclass is indented under subclass 118. Subject matter
wherein one access sequence to the cache memory is started
before a prior access sequence is completed.
SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems:
Processing- Processing Architectures and Instruction
Processing (e.g., Processors) 205.
Subclass:
141
Coherency:
This subclass is indented under subclass 118. Subject matter
further comprising means or steps not specifically covered
above for assuring that the data stored in the cache memory
and those of the main memory are either identical or
controlled so that stale and current data are not confused
with each other.
(1) Note. The subject matter in this subclass is also
called cache consistency or cache currency in the art.
SEE OR SEARCH THIS CLASS, SUBCLASS:
161 for various reliability methods under accessing and
control allowed by the (6) Note for subclass 100 above, such
as archiving and backup.
SEE OR SEARCH CLASS:
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 200 for file and
database maintenance systems including data coherency in
database or file systems and subclasses 530+ for developing
or changing a document wherein one or more elements of
document are added, deleted, or modified, or including means
or steps for storing the resultant altered document or the
alterations.
714, Error Detection/Correction and Fault Detection/Recovery,
1 for reliability and availability in digital data
processing systems, per se, including subclasses 5+ for
memory or peripheral subsystem affected fault recovery.
Subclass:
142
Write-through:
This subclass is indented under subclass 141. Subject matter
where, as contents of the cache are changed, the changes are
also posted to main memory substantially simultaneously.
Subclass:
143
Write-back:
This subclass is indented under subclass 141. Subject matter
where, as contents of the cache are changed, the changes are
not posted to main memory immediately, but rather changes to
a block are posted upon the occurrence of a predetermined
event.
Subclass:
144
Cache status data bit:
This subclass is indented under subclass 141. Subject matter
wherein coherency for each unit or block of data includes
associated identifier bit(s) to indicate the validity status
of an associated cached location.
(1) Note. For this subclass, validity status bits can
indicate whether data are modified, valid, dirty, etc.
Subclass:
145
Access control bit:
This subclass is indented under subclass 141. Subject matter
wherein each unit or block of memory or cache includes
associated identifier bit(s) to indicate ownership of or
restricted access to the unit or block.
(1) Note. For this subclass, access control bits can
indicate whether the associated cached location is exclusive,
shared, read only, locked, etc.
Subclass:
146
Snooping:
This subclass is indented under subclass 141. Subject matter
further comprising cache memory monitoring an associated
address bus to determine if access to a cached location
occurs by another cache memory or other user (e.g., DMA,
peripherals, etc.).
SEE OR SEARCH CLASS:
710, Electrical Computers And Digital Data Processing
Systems: Input/Output, 100 for system intraconnecting,
particularly subclasses 107+ for bus access regulating.
Subclass:
147
Shared memory area:
This subclass is indented under subclass 100. Subject matter
wherein at least a portion of the memory being accessed or
controlled is solid-state memory that iscommon to a plurality
of users (e.g., a CPU and a DMA controller, multiple CPUs,
etc.) or a plurality of tasks (e.g., in a multitasking
system) or both.
SEE OR SEARCH CLASS:
395, Information Processing System Organization, subclass
200.43 for a plurality of computers transferring data
through one or more memories accessible by the plurality of
computers; subclass 496 for memory access pipelining; and
subclasses 672+ for process scheduling involving balancing
the work load or resources, memory use, register use,
resource availability, time constraints, semaphores, and
mutual exclusion mechanisms used for programs or process
synchronization.
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 1, 100+, and 200+ for
database access, schema, and maintenance.
Subclass:
148
Plural shared memories:
This subclass is indented under subclass 147. Subject matter
wherein plural independent memories are shared.
Subclass:
149
Multiport memory:
This subclass is indented under subclass 147. Subject matter
including means or steps for controlling shared memory
capable of supporting a plurality of simultaneous read
accesses.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass
230.05 for multiple port access devices.
Subclass:
150
Simultaneous access regulation:
This subclass is indented under subclass 147. Subject matter
including provisions for controlling simultaneous memory
access requests.
SEE OR SEARCH CLASS:
710, Electrical Computers And Digital Data Processing
Systems: Input/Output, 36 for I/O access regulating;
subclasses 107+ for access regulating and arbitration within
a digital data processing system; subclasses 200 through 244
for generalized locking, polling, access arbitrating; and
subclasses 260+ for interrupt processing.
Subclass:
151
Prioritized access regulation:
This subclass is indented under subclass 147. Subject matter
including provisions for assigning priority for use in
handling simultaneous memory access requests.
SEE OR SEARCH CLASS:
395, Information Processing System Organization, subclass 673
for priority scheduling of process (e.g., deciding which
resources to use, deciding which jobs to do first and what
order to do them; scheduling constraints may include resource
characteristics such as performance, availability, data
coherency, etc.).
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 36 for I/O access regulating;
subclasses 107+ for access regulating and arbitration within
a digital data processing system; and subclasses 200 through
269 for generalized locking, polling, access arbitrating, and
interrupt processing.
Subclass:
152
Memory access blocking:
This subclass is indented under subclass 147. Subject matter
including provisions for selectively restricting access to
memory areas.
SEE OR SEARCH CLASS:
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 36 for I/O access regulating;
subclasses 107+ for access regulating and arbitration within
a digital data processing system; and subclasses 200 through
244 for generic access locking, access regulating, or access
arbitration in data processing system.
Subclass:
153
Shared memory partitioning:
This subclass is indented under subclass 147. Subject matter
further comprising means for dividing or segmenting a given
logical shared memory area into independent sections or
domains.
SEE OR SEARCH CLASS:
395, Information Processing System Organization, subclasses
670+ for processing task management, per se, in particular
subclasses 677 and 678 for multi-tasking and context
switching; and subclasses 680+ and 701 through 712 for
various operating system functions, per se.
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 1 for database
management and file management systems including significant
addressing, retrieval, or manipulation of information
contained within a database of a digital data processing
system or computer including searching, query processing,
information locating and retrieval techniques from a file or
database; and subclasses 200+ for file maintenance
operations, allocating or deallocating memory space to files,
garbage collection, and hierarchical or tree filling
systems.
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), subclass 228 for processing control and
instruction processing for context preserving; subclass 229
for processing control and instruction processing for mode
switch or change.
713, Electrical Computers and Digital Processing Systems:
Support, 200 for + for system initialization or
configuration (e.g., initializing, set up, configuration or
resetting), subclass 100 for reconfiguring (e.g., changing
system settings).
Subclass:
154
Control technique:
This subclass is indented under subclass 100. Subject matter
including particular means or steps for controlling memory
accesses not specifically provided for above.
SEE OR SEARCH CLASS:
714, Error Detection/Correction and Fault Detection/Recovery,
subclass 702 for memory access, subclasses 710+ for
replacement with spare memory component or portion of memory
component, subclasses 763+ for memory testing and memory
accessing with error correction.
Subclass:
155
Read-modify-write (RMW):
This subclass is indented under subclass 154. Subject matter
including provisions for performing an access operation where
the contents of a given memory location are read and then
overwritten in a single access operation.
Subclass:
156
Status storage:
This subclass is indented under subclass 154. Subject matter
including provisions for storing data associated with memory
accessing and control.
(1) Note. Examples of status data include control status
words, program status words, etc.
Subclass:
157
Interleaving:
This subclass is indented under subclass 154. Subject matter
wherein consecutive memory addresses are in nonadjacent
physical locations.
SEE OR SEARCH THIS CLASS, SUBCLASS:
5 for interleaving in combination with multiple memory
modules with significant addressing.
127 for cache interleaving where consecutive cache memory
locations are located in different memory components.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass
230.03 and 230.04 for subject matter including plural banks
or blocks and alternating between them.
Subclass:
158
Prioritizing:
This subclass is indented under subclass 154. Subject matter
including banks or modules which are arranged so that a given
physical memory element has access priority over another.
Subclass:
159
Entry replacement strategy:
This subclass is indented under subclass 154. Subject matter
including provisions for determining when the data stored in
a particular memory location may be replaced.
SEE OR SEARCH THIS CLASS, SUBCLASS:
133 for cache entry replacement strategies.
Subclass:
160
Least recently used (LRU):
This subclass is indented under subclass 159. Subject matter
wherein the determination is made based upon the time since
the last access to the contents of a given location.
Subclass:
161
Archiving:
This subclass is indented under subclass 154. Subject matter
wherein the control technique prevents the corruption, loss,
alteration, or disclosure of data by storing.
SEE OR SEARCH CLASS:
380, Cryptography, 3 for stored information access or copy
prevention (e.g., software program protection or computer
virus detection) in combination with data encryption, and
subclasses 22 through 25 and 50 for electric signal
modification, and other appropriate subclasses.
395, Information Processing System Organization, subclass 712
for local and remote software loading, copying, or installing
of a software (e.g., operating system, application program,
and other executable program) onto a target storage medium
such as a hard disk, tape drive, or other memory devices.
714, Error Detection/Correction and Fault Detection/Recovery,
1 for diagnostic testing or monitoring of a digital data
processing system for reliability purposes comprising power
fail-safe functions, fault detection, or anticipation of a
failure; more specifically, subclasses 5+ for memory or
peripheral subsystem affected recovery, subclass 42 for
memory component fault, and subclass 54 for storage content
error detection or notification, subclasses 5+ and 718+ for
reliability and availability in memory accessing and control
such as isolating failed memory and storing redundant data
with recitation of the recovery, fault, or failure.
Subclass:
162
Backup:
This subclass is indented under subclass 161. Subject matter
wherein a verbatim redundant copy of the data is made.
SEE OR SEARCH THIS CLASS, SUBCLASS:
165 for movement or transfers of data amongst locations
within a same memory level.
SEE OR SEARCH CLASS:
714, Error Detection/Correction and Fault Detection/Recovery,
5 and 718+ for reliability and availability in memory
accessing and control such as isolating failed memory and
storing redundant data with recitation of the recovery,
fault, or failure.
Subclass:
163
Access limiting:
This subclass is indented under subclass 154. Subject matter
wherein memory entry is restricted.
SEE OR SEARCH CLASS:
380, Cryptography, subclass 4 for stored digital data access
or copy prevention in combination with data encryption (e.g.,
software program protection or computer virus detection in
combination with data encryption), and subclasses 23+ for
authentication systems using encrypted transmission.
455, Telecommunications, subclass 26.1 for subject matter
which blocks access to a signal source or otherwise limits
usage of modulated carrier equipment.
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 36 for access regulating of
peripheral to computer or vice versa; subclasses 107+ for
regulating access of processors or memories to a bus; and
subclasses 200 through 244 for generic access locking, access
regulating, or access arbitration in data processing system.
713, Electrical Computers and Digital Processing Systems:
Support, 200 for security in computers or digital data
processing systems.
714, Error Detection/Correction and Fault Detection/Recovery,
763 for memory access block coding and subclass 805 for
storage accessing error/fault detection techniques.
Subclass:
164
With password or key:
This subclass is indented under subclass 163. Subject matter
wherein authorization code information (e.g., password, key
other than encryption key, etc.) is required for memory
access.
(1) Note. This subclass does not provide for
cryptos:graphic keys. See below.
SEE OR SEARCH CLASS:
380, Cryptography, subclass 4 for stored digital data access
or copy prevention in combination with data encryption (e.g.,
software program protection or computer virus detection in
combination with data encryption).
455, Telecommunications, subclass 26.1 for subject matter
which blocks access to a signal source or otherwise limits
usage of modulated carrier equipment.
705, Data Processing: Financial, Business Practice,
Management, or Cost/Price Determination, subclass 18 for
handling security or user identification provision to either
prevent unauthorized use or access.
713, Electrical Computers and Digital Processing Systems:
Support, 200 for security in a digital data processing
system requiring password.
714, Error Detection/Correction and Fault Detection/Recovery,
763 for memory access block coding and subclass 805 for
storage accessing error/fault detection techniques.
Subclass:
165
Internal relocation:
This subclass is indented under subclass 154. Subject matter
including provisions for moving or copying data from one
location in a given memory to another location in the given
memory or another memory at the same hierarchical level.
(1) Note. This subclass does not provide for DMA. See
below.
SEE OR SEARCH CLASS:
710, Electrical Computers And Digital Data Processing
Systems: Input/Output, 22 for transferring data via the I/O
mechanism of DMA.
Subclass:
166
Resetting:
This subclass is indented under subclass 154. Subject matter
including provisions for clearing or initializing the
contents of a given memory location.
(1) Note. This subclass provides for setting a portion of
memory to an initial condition (e.g., filling all locations
with zeros).
SEE OR SEARCH CLASS:
713, Electrical Computers and Digital Processing Systems:
Support, subclass 1 for digital data processing system
initialization or configuration (e.g., initializing, setup,
configuration, or resetting) allocating extended or expanded
memory, speci device drivers, paths, files, buffers, disk
management, etc.; subclass 2 for loading initialization
program (e.g., booting, BIOS, IPL, bootstrap, etc.); and
subclass 100 for reconfiguring (e.g., changing system
settings) of system settings, per se.
Subclass:
167
Access timing:
This subclass is indented under subclass 100. Subject matter
including provisions for controlling or coordinating the
sequence of operations that make up a memory access.
SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, subclasses 93-98
for clocking or synchronizing of logic stages or gates.
370, Multiplex Communications, subclass 507 wherein the
clock frequency adjustment of one station is based upon
information about status of clock signals originating at
other stations of the system.
375, Pulse or Digital Communications, 354 for synchronizing
the operation of pulse or digital receiving or transmitting
mechanisms.
395, Information Processing System Organization, subclass
200.78 for multi-computer synchronization in a network;
subclasses 670+ for task and process scheduling, per se.
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, subclass 61 for synchronous data
transfer in I/O process timing.
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), subclasses 245-248 for processing sequence
control.
713, Electrical Computers and Digital Processing Systems:
Support, 400 for details relating to the timing control or
timing regulation of any one or combination of digital data
processing system components according to a periodic sequence
of clock/ timing pulses(e.g., synchronous time control, time
delay, cycle control, cycle steal, etc.).
714, Error Detection/Correction and Fault Detection/Recovery,
subclass 12 for fault recovery synchronization of
redundantly operating processors.
Subclass:
168
Concurrent accessing:
This subclass is indented under subclass 167. Subject matter
further including means or steps wherein multiple memory
accesses are initiated substantially simultaneously.
SEE OR SEARCH CLASS:
395, Information Processing System Organization, 677 for
multitasking, time sharing/slicing.
Subclass:
169
Memory access pipelining:
This subclass is indented under subclass 167. Subject matter
further including means or steps wherein a first access to
memory is initiated before a second access is completed.
(1) Note. Pipelined instruction data processing is
classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS
notes below.
SEE OR SEARCH CLASS:
395, Information Processing System Organization, and subclass
670 for task management and control related to process or job
execution.
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), 205 for instruction fetching, subclasses 214+
for instruction issuing, subclasses 233+ for branching
instruction processing.
713, Electrical Computers and Digital Processing Systems:
Support, subclass 2 for loading initializing program.
Subclass:
170
Memory configuring:
This subclass is indented under subclass 100. Subject matter
in which the allocation of memory space is specified or the
layout is automatically determined.
(1) Note. Configuration at booting via software is
classified elsewhere in this class. See the SEARCH THIS
CLASS, SUBCLASS notes below.
(2) Note. Assigning operating characteristics to
peripherals is classified elsewhere in this class. See the
SEARCH THIS CLASS, SUBCLASS notes below.
SEE OR SEARCH CLASS:
395, Information Processing System Organization, subclass
200.5 for network computer configuring; subclasses 670+ for
task management, per se, in particular subclass 674 for
resource allocation (e.g., deciding how best to use the
available resources to get the job done) and subclasses 677
and 678 for multi-tasking and context switching.
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 1 for database
management and file management systems including significant
addressing, retrieval, or manipulation of information
contained within a database of a digital data processing
system or computer including searching, query processing,
information locating and retrieval techniques from a file or
database; and subclasses 200+ for file maintenance
operations, allocating or deallocating memory space to files,
garbage collection, and hierarchical or tree filling
systems.
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 8 for assigning operating
characteristics to peripherals or peripheral configuring and
subclass 104 for utilizing a hardware structure for providing
to a digital data processing system component the arrangement
of the digital data processing system including
characteristics of the digital data processing system's
components.
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), subclass 228 for processing control and
instruction processing for context preserving, subclass 229
for processing control and instruction processing for mode
switch or change.
713, Electrical Computers and Digital Processing Systems:
Support, 1 for digital data processing system initialization
or configuration ( e.g., initializing, set up, configuration,
or resetting) allocating extended or expanded memory,
specifying device driver, path, file, buffer, disk
management, etc.; subclass 100 for reconfiguring of system
setting, per se.
714, Error Detection/Correction and Fault Detection/Recovery,
3 for reconfiguring in the event of a fault under fault
recovery, reliability, and availability.
Subclass:
171
Based on data size:
This subclass is indented under subclass 170. Subject matter
comprising means or steps for allocating memory space based
on the amount of storage space required.
Subclass:
172
Based on component size:
This subclass is indented under subclass 170. Subject matter
comprising means or steps for allocating memory based on the
size of each physical solid-state memory.
Subclass:
173
Memory partitioning:
This subclass is indented under subclass 170. Subject matter
further comprising means for dividing or segmenting a given
logical memory into independent sections or domains.
Subclass:
200
ADDRESS FORMATION:
This subclass is indented under the class definition.
Subject matter comprising means or steps for determining or
modifying a value which specifies a location in at least one
memory.
(1) Note. The subject matter of this subclass and the
subclasses thereunder includes, for example, virtual memory
addressing, address translation, translation look-aside
buffers (TLBs), boundary checking, and page-mode addressing.
(2) Note. The subject matter also includes deriving new
address data from existing address data.
(3) Note. The location in memory may include data for
forming further an address (e.g., address mapping is
classified herein).
(4) Note. Means or steps for addressing or for storing data
in one or more memory cells of a storage medium having one or
more specific, internal cell elements is classified
elsewhere. See the SEARCH CLASS notes below.
SEE OR SEARCH THIS CLASS, SUBCLASS:
1 for addressing combined with specific memory
configurations (e.g., extended/expanded memory, cache memory,
dynamic memory, etc.).
3 for cache memory addressing.
101 through 116, for storage accessing and control for
various memory compositions (e.g., ROM, RAM, CAM, dynamic,
detachable, bubble, etc.) with more than nominal data
processing.
SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, subclasses 104-108
for digital logic decoding circuits in general.
340, Communications: Electrical, 825.52 for selective
communication addressing and subclasses 825.79+ for selective
matrix which may be used for control or as a switching
means.
345, Computer Graphics Processing, Operator Interface
Processing, and Selective Visual Display Systems, 507 for
processing indices to locations (or addresses) of stored data
elements in a computer s:graphic processing system.
360, Dynamic Magnetic Information Storage or Retrieval,
subclass 72.2 for addressing and control of recording
mechanism to locate the selected area.
365, Static Information Storage and Retrieval, 189.01 for
read/write circuits and subclasses 230.01+ for addressing of
addressable, static single storage elements or plural
elements of the same type.
369, Dynamic Information Storage or Retrieval, various
subclasses for record carriers and systems wherein
information is stored and retrieved by interaction with a
medium and there is relative motion between a medium and a
transducer. Particularly, see subclasses 30-34 for
selective addressing of dynamic storage medium.
370, Multiplex Communications, appropriate subclasses for
multiplex switching techniques similar to addressing and the
handling of memory information signals (e.g., 351 for
packetized multiplexed communications).
704, Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression, 2
for memory control scheme combined with linguistics.
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 1 for database
management and file management systems including significant
addressing, retrieval, or manipulation of information
contained within a database of a digital data processing
system or computer including searching, query processing,
information locating and retrieval techniques from a file or
database; subclasses 100+ for database schema types; and
subclasses 200+ for file maintenance operations, allocating
or deallocating memory space to files, garbage collection,
and hierarchical or tree filling systems.
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 3 for Input/Output addressing;
subclass 9 for address assignment for configuring
peripherals; subclasses 22+ for direct memory accessing
including addressing techniques; and subclasses 131+ for
system intraconnecting switching.
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), 208 for instruction decoding involving start or
initial address generation ; subclass 230 for generating the
address of the next micro-instruction.
Subclass:
201
Slip control, misaligning, boundary alignment:
This subclass is indented under subclass 200. Subject matter
wherein the value determination takes into account a memory
size constraint.
(1) Note. This subclass will accept range or limit
checking, boundary crossing, and related memory boundary
issues (e.g., (a) handling a boundary fixed length field to
accommodate data size or position and boundary checking and
(b) incrementing addresses within a page).
Subclass:
202
Address mapping (e.g., conversion, translation):
This subclass is indented under subclass 200. Subject matter
including translating (i.e., converting) processor memory
address data to physical memory address data through a
mechanism which defines a correspondence between the
addresses.
(1) Note. The subject matter in this and the indented
subclasses is aimed at determining a physical address using a
mapping technique.
(2) Note. Classification here is proper for direct mapping
for a segmented memory not being used in a virtual memory
system.
Subclass:
203
Virtual addressing:
This subclass is indented under subclass 202. Subject matter
wherein the mapping allows an application to view available
memory resources as a uniform primary memory.
SEE OR SEARCH THIS CLASS, SUBCLASS:
6 for address mapping for virtual machines.
Subclass:
204
Predicting, look-ahead:
This subclass is indented under subclass 203. Subject matter
wherein means or steps are utilized for optimizing address
determination by, for example, anticipating a next address or
prefetching addresses.
SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), 205 for instruction fetching, subclass 207 for
profetching of instructions and 233+ for branch prediction.
Subclass:
205
Directories and tables (e.g., DLAT, TLB):
This subclass is indented under subclass 204. Subject matter
wherein a memory space is employed for registering indexes
and the like to real or physical address spaces in a
predicting or look-ahead arrangement.
(1) Note. A directory table is a mechanism for storing
virtual (i.e., logical) to physical (i.e., real, absolute)
address translation entries that are used in combination with
methods of predicting or prefetching.
(2) Note. DLAT is a term of art referring to Directory
Look-Aside Table; TLB is a term of art referring to
Translation Look-Aside Buffer.
Subclass:
206
Translation tables (e.g., segment and page table or map):
This subclass is indented under subclass 203. Subject matter
wherein directories (e.g., maps) are employed for converting
address data in a first form (e.g., virtual, logical) to
address data in a second form (e.g., physical, absolute).
(1) Note. This subclass and its indented subclasses are
intended for generalized applications of tables not
classifiable in the combinations above.
(2) Note. This area also provides for mechanisms for
storing virtual (i.e., logical) to physical (i.e., real,
absolute) address translation entries that are of general use
in virtual memory.
(3) Note. This subclass will accept table walking which
generally requires accesses to main memory.
Subclass:
207
Directory tables (e.g., DLAT, TLB):
This subclass is indented under subclass 206. Subject matter
wherein a memory space is employed for registering indexes
and the like to real or physical address spaces.
(1) Note. These mechanisms convert address data from a
virtual address to a physical address without the need for
accessing translation tables in main memory (e.g., utilizing
cache for virtual to physical translation).
(2) Note. DLAT is a term of art referring to Directory
Look-Aside Table; TLB is a term of art referring to
Translation Look-Aside Buffer.
SEE OR SEARCH THIS CLASS, SUBCLASS:
3 for cache memory addressing.
Subclass:
208
Segment or page table descriptor:
This subclass is indented under subclass 206. Subject matter
wherein an entry, word, or other data is maintained and is
utilized in the translation.
Subclass:
209
Including plural logical address spaces, pages, segments,
blocks:
This subclass is indented under subclass 203. Subject matter
wherein portions of memory are organized or managed in
accordance with a predetermined mapping scheme.
(1) Note. This subclass includes art directed to addressing
variable-sized pages, segments, and blocks.
Subclass:
210
Resolving conflict, coherency, or synonym problem:
This subclass is indented under subclass 202. Subject matter
including compensating for situations when addresses map to
the same location (e.g., synonym problems or alias
addresses).
SEE OR SEARCH CLASS:
714, Error Detection/Correction and Fault Detection/Recovery,
subclass 180 for reliability and availability in general in
digital data processing systems.
Subclass:
211
Address multiplexing or address bus manipulation:
This subclass is indented under subclass 200. Subject matter
including address bus modifying, multiplexing addresses, or
adapting to various bus widths.
SEE OR SEARCH CLASS:
710, Electrical Computers and Digital Data Processing
Systems: Input/Output, 101 for bus extending or expanding
and subclasses 126+ for bus architectures.
Subclass:
212
Varying address bit-length or size:
This subclass is indented under subclass 200. Subject matter
wherein bits are added or subtracted from existing address
data to generate other address data.
Subclass:
213
Generating prefetch, look-ahead, jump, or predictive
address:
This subclass is indented under subclass 200. Subject matter
wherein look-ahead, predictive, or jump address data are
formed.
(1) Note. Prefetching, look-ahead, etc., for virtual memory
addressing are classified elsewhere.
SEE OR SEARCH THIS CLASS, SUBCLASS:
203 for virtual memory addressing.
SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), 205 and 207 and 233+ respectively.
Subclass:
214
Operand address generation:
This subclass is indented under subclass 200. Subject matter
wherein data relevant to an instruction and used by an
instruction are used to form the address.
SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), subclasses 200-219, 220+ and 300 for instruction
processing, particularly subclasses 233 through 244 for
branching instruction processing.
Subclass:
215
In response to microinstruction:
This subclass is indented under subclass 200. Subject matter
wherein microcode is stored in memory and particular
addressing mechanisms at the microinstruction level are
employed.
SEE OR SEARCH CLASS:
712, Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g.,
Processors), particularly subclasses 200-219, 220+ and 300
for instruction processing, particularly 245+ for
microsequencing processing; and subclasses 1+ for digital
data processing system architecture.
Subclass:
216
Hashing:
This subclass is indented under subclass 200. Subject matter
wherein an address value (i.e., key other than an encryption
key) is manipulated to form an index value.
(1) Note. This subclass does not provide for
cryptos:graphic keys. See below.
SEE OR SEARCH CLASS:
380, Cryptography, subclass 4 for stored digital data access
or copy prevention in combination with data encryption (e.g.,
software program protection or computer virus detection in
combination with data encryption).
707, Data Processing: Database and File Management, Data
Structures, or Document Processing, 1 for database searching
utilizing hashing.
713, Electrical Computers and Digital Processing Systems:
Support, 200 for security in a digital data processing
system requiring password.
Subclass:
217
Generating a particular pattern/sequence of addresses:
This subclass is indented under subclass 200. Subject matter
wherein values specifying memory locations are determined
according to a predetermined algorithm.
SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, subclass
230.03 and 230.04 for subject matter including plural banks
or blocks and alternating between them.
714, Error Detection/Correction and Fault Detection/Recovery,
subclasses 718-720 for testing memories utilizing patterns
of addresses and data.
Subclass:
218
Sequential addresses generation:
This subclass is indented under subclass 217. Subject matter
wherein the pattern created is seriatim.
SEE OR SEARCH CLASS:
377, Electrical Pulse Counters, Pulse Dividers, or Shift
Registers: Circuits and Systems, appropriate subclasses for
generic pulse counting circuits and systems.
Subclass:
219
Incrementing, decrementing, or shiftingcircuitry:
This subclass is indented under subclass 200. Subject matter
utilizing particular hardware that adds by 1, subtracts by 1,
and multiplies or divides by 2n (where n is an integer).
SEE OR SEARCH CLASS:
377, Electrical Pulse Counters, Pulse Dividers, or Shift
Registers: Circuits and Systems, appropriate subclasses for
generic pulse counting circuits and systems.
Subclass:
220
Combining two or more values to create address:
This subclass is indented under subclass 200. Subject matter
wherein results from the interaction of two or more other
data provide the address (e.g., generalized indirect
addressing, indexing, prefixing, base + sag/tag + set, bit
insertion).
Subclass:
221
Using table:
This subclass is indented under subclass 200. Subject matter
having a memory space of general utility for registering
indexes and like data related to address generation (e.g.,
fixed offsets, conditions, or status).
SEE OR SEARCH THIS CLASS, SUBCLASS:
202 for tables used in mapping or translating.
Information Products Division -- Contacts
Questions regarding this report should be directed to:
U.S. Patent and Trademark Office
Information Products Division
PK3- Suite 441
Washington, DC 20231
tel: (703) 306-2600
FAX: (703) 306-2737
email: oeip@uspto.gov
Last Modified: 6 October 2000