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ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTRUCTION PROCESSING (E.G., PROCESSORS)
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1 | ![[Patents]](../gifs/ps.gif) | PROCESSING ARCHITECTURE |
2 | ![[Patents]](../gifs/ps.gif) | . Vector processor |
3 | ![[Patents]](../gifs/ps.gif) | . . Scalar/vector processor interface |
4 | ![[Patents]](../gifs/ps.gif) | . . Distributing of vector data to vector registers |
5 | ![[Patents]](../gifs/ps.gif) | . . . Masking to control an access to data in vector register |
6 | ![[Patents]](../gifs/ps.gif) | . . Controlling access to external vector data |
7 | ![[Patents]](../gifs/ps.gif) | . . Vector processor operation |
8 | ![[Patents]](../gifs/ps.gif) | . . . Sequential |
9 | ![[Patents]](../gifs/ps.gif) | . . . Concurrent |
10 | ![[Patents]](../gifs/ps.gif) | . Array processor |
11 | ![[Patents]](../gifs/ps.gif) | . . Array processor element interconnection |
12 | ![[Patents]](../gifs/ps.gif) | . . . Cube or hypercube |
13 | ![[Patents]](../gifs/ps.gif) | . . . Partitioning |
14 | ![[Patents]](../gifs/ps.gif) | . . . Processing element memory |
15 | ![[Patents]](../gifs/ps.gif) | . . . Reconfiguring |
16 | ![[Patents]](../gifs/ps.gif) | . . Array processor operation |
17 | ![[Patents]](../gifs/ps.gif) | . . . Application specific |
18 | ![[Patents]](../gifs/ps.gif) | . . . Data flow array processor |
19 | ![[Patents]](../gifs/ps.gif) | . . . Systolic array processor |
20 | ![[Patents]](../gifs/ps.gif) | . . . Multimode (e.g., MIMD to SIMD, etc.) |
21 | ![[Patents]](../gifs/ps.gif) | . . . Multiple instruction, Multiple data (MIMD) |
22 | ![[Patents]](../gifs/ps.gif) | . . . Single instruction, multiple data (SIMD) |
23 | ![[Patents]](../gifs/ps.gif) | . Superscalar |
24 | ![[Patents]](../gifs/ps.gif) | . Long instruction word |
25 | ![[Patents]](../gifs/ps.gif) | . Data driven or demand driven processor |
26 | ![[Patents]](../gifs/ps.gif) | . . Detection/pairing based on destination, ID tag, or data |
27 | ![[Patents]](../gifs/ps.gif) | . . Particular data driven memory structure |
28 | ![[Patents]](../gifs/ps.gif) | . Distributed processing system |
29 | ![[Patents]](../gifs/ps.gif) | . . Interface |
30 | ![[Patents]](../gifs/ps.gif) | . . Operation |
31 | ![[Patents]](../gifs/ps.gif) | . . . Master/slave |
32 | ![[Patents]](../gifs/ps.gif) | . Microprocessor or multichip or multimodule processor having sequential program control |
33 | ![[Patents]](../gifs/ps.gif) | . . Having multiple internal buses |
34 | ![[Patents]](../gifs/ps.gif) | . . Including coprocessor |
35 | ![[Patents]](../gifs/ps.gif) | . . . Digital Signal processor |
36 | ![[Patents]](../gifs/ps.gif) | . . Application specific |
37 | ![[Patents]](../gifs/ps.gif) | . . Programmable (e.g., EPROM) |
38 | ![[Patents]](../gifs/ps.gif) | . . Offchip interface |
39 | ![[Patents]](../gifs/ps.gif) | . . . Externally controlled internal mode switching via pin |
40 | ![[Patents]](../gifs/ps.gif) | . . . External sync or interrupt signal |
41 | ![[Patents]](../gifs/ps.gif) | . . RISC |
42 | ![[Patents]](../gifs/ps.gif) | . . Operation |
43 | ![[Patents]](../gifs/ps.gif) | . . . Mode switching |
200 | ![[Patents]](../gifs/ps.gif) | ARCHITECTURE BASED INSTRUCTION PROCESSING |
201 | ![[Patents]](../gifs/ps.gif) | . Data flow based system |
202 | ![[Patents]](../gifs/ps.gif) | . Stack based computer |
203 | ![[Patents]](../gifs/ps.gif) | . Multiprocessor instruction |
204 | ![[Patents]](../gifs/ps.gif) | INSTRUCTION ALIGNMENT |
205 | ![[Patents]](../gifs/ps.gif) | INSTRUCTION FETCHING |
206 | ![[Patents]](../gifs/ps.gif) | . Of multiple instructions simultaneously |
207 | ![[Patents]](../gifs/ps.gif) | . Prefetching |
208 | ![[Patents]](../gifs/ps.gif) | INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED) |
209 | ![[Patents]](../gifs/ps.gif) | . Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.) |
210 | ![[Patents]](../gifs/ps.gif) | . Decoding instruction to accommodate variable length instruction or operand |
211 | ![[Patents]](../gifs/ps.gif) | . Decoding instruction to generate an address of a microroutine |
212 | ![[Patents]](../gifs/ps.gif) | . Decoding by plural parallel decoders |
213 | ![[Patents]](../gifs/ps.gif) | . Predecoding of instruction component |
214 | ![[Patents]](../gifs/ps.gif) | INSTRUCTION ISSUING |
215 | ![[Patents]](../gifs/ps.gif) | . Simultaneous issuance of multiple instructions |
216 | ![[Patents]](../gifs/ps.gif) | DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION |
217 | ![[Patents]](../gifs/ps.gif) | . Scoreboarding, reservation station, or aliasing |
218 | ![[Patents]](../gifs/ps.gif) | . Commitment control or register bypass |
219 | ![[Patents]](../gifs/ps.gif) | . Reducing an impact of a stall or pipeline bubble |
220 | ![[Patents]](../gifs/ps.gif) | PROCESSING CONTROL |
221 | ![[Patents]](../gifs/ps.gif) | . Arithmetic operation instruction processing |
222 | ![[Patents]](../gifs/ps.gif) | . . Floating point or vector |
223 | ![[Patents]](../gifs/ps.gif) | . Logic operation instruction processing |
224 | ![[Patents]](../gifs/ps.gif) | . . Masking |
225 | ![[Patents]](../gifs/ps.gif) | . Processing control for data transfer |
226 | ![[Patents]](../gifs/ps.gif) | . Instruction modification based on condition |
227 | ![[Patents]](../gifs/ps.gif) | . Specialized instruction processing in support of testing, debugging, emulation |
228 | ![[Patents]](../gifs/ps.gif) | . Context preserving (e.g., context swapping, checkpointing, register windowing |
229 | ![[Patents]](../gifs/ps.gif) | . Mode switch or change |
230 | ![[Patents]](../gifs/ps.gif) | . Generating next microinstruction address |
231 | ![[Patents]](../gifs/ps.gif) | . Detecting end or completion of microprogram |
232 | ![[Patents]](../gifs/ps.gif) | . Hardwired controller |
233 | ![[Patents]](../gifs/ps.gif) | . Branching (e.g., delayed branch, loop control, branch predict, interrupt) |
234 | ![[Patents]](../gifs/ps.gif) | . . Conditional branching |
235 | ![[Patents]](../gifs/ps.gif) | . . . Simultaneous parallel fetching or executing of both branch and fall-through path |
236 | ![[Patents]](../gifs/ps.gif) | . . . Evaluation of multiple conditions or multiway branching |
237 | ![[Patents]](../gifs/ps.gif) | . . . Prefetching a branch target (i.e., look ahead) |
238 | ![[Patents]](../gifs/ps.gif) | . . . . Branch target buffer |
239 | ![[Patents]](../gifs/ps.gif) | . . . Branch prediction |
240 | ![[Patents]](../gifs/ps.gif) | . . . . History table |
241 | ![[Patents]](../gifs/ps.gif) | . . Loop execution |
242 | ![[Patents]](../gifs/ps.gif) | . . To macro-instruction routine |
243 | ![[Patents]](../gifs/ps.gif) | . . To microinstruction subroutine |
244 | ![[Patents]](../gifs/ps.gif) | . . Exeception processing (e.g., interrupts and traps) |
245 | ![[Patents]](../gifs/ps.gif) | . Processing sequence control (i.e., microsequencing) |
246 | ![[Patents]](../gifs/ps.gif) | . . Plural microsequencers (e.g., dual microsequencers) |
247 | ![[Patents]](../gifs/ps.gif) | . . Multilevel microcontroller (e.g., dual-level control store) |
248 | ![[Patents]](../gifs/ps.gif) | . . Writable/changeable control store architecture |
300 | ![[Patents]](../gifs/ps.gif) | BYTE-WORD REARRANGING, BIT-FIELD INSERTION OR EXTRACTION, STRING LENGTH DETECTING, OR SEQUENCE DETECTING |