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ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MEMORY
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1 | ![[Patents]](../gifs/ps.gif) | ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR SYSTEM |
2 | ![[Patents]](../gifs/ps.gif) | . Addressing extended or expanded memory |
3 | ![[Patents]](../gifs/ps.gif) | . Addressing cache memories |
4 | ![[Patents]](../gifs/ps.gif) | . Dynamic-type storage device (e.g., disk, tape, drum) |
5 | ![[Patents]](../gifs/ps.gif) | . For multiple memory modules (e.g., banks, interleaved memory) |
6 | ![[Patents]](../gifs/ps.gif) | . Virtual machine memory addressing |
100 | ![[Patents]](../gifs/ps.gif) | STORAGE ACCESSING AND CONTROL |
101 | ![[Patents]](../gifs/ps.gif) | . Specific memory composition |
102 | ![[Patents]](../gifs/ps.gif) | . . Solid-state read only memory (ROM) |
103 | ![[Patents]](../gifs/ps.gif) | . . . Programmable read only memory (PROM, EEPROM, etc.) |
104 | ![[Patents]](../gifs/ps.gif) | . . Solid-state random access memory (RAM) |
105 | ![[Patents]](../gifs/ps.gif) | . . . Dynamic random access memory |
106 | ![[Patents]](../gifs/ps.gif) | . . . . Refresh scheduling |
107 | ![[Patents]](../gifs/ps.gif) | . . Ferrite core |
108 | ![[Patents]](../gifs/ps.gif) | . . Content addressable memory (CAM) |
109 | ![[Patents]](../gifs/ps.gif) | . . Shift register memory |
110 | ![[Patents]](../gifs/ps.gif) | . . . Circulating memory |
111 | ![[Patents]](../gifs/ps.gif) | . . Accessing dynamic storage device |
112 | ![[Patents]](../gifs/ps.gif) | . . . Direct access storage device (DASD) |
113 | ![[Patents]](../gifs/ps.gif) | . . . . Caching |
114 | ![[Patents]](../gifs/ps.gif) | . . . . Arrayed (e.g., RAIDs) |
115 | ![[Patents]](../gifs/ps.gif) | . . Detachable memory |
116 | ![[Patents]](../gifs/ps.gif) | . . Bubble memory |
117 | ![[Patents]](../gifs/ps.gif) | . Hierarchical memories |
118 | ![[Patents]](../gifs/ps.gif) | . . Caching |
119 | ![[Patents]](../gifs/ps.gif) | . . . Multiple caches |
120 | ![[Patents]](../gifs/ps.gif) | . . . . Parallel caches |
121 | ![[Patents]](../gifs/ps.gif) | . . . . Private caches |
122 | ![[Patents]](../gifs/ps.gif) | . . . . Hierarchical caches |
123 | ![[Patents]](../gifs/ps.gif) | . . . . User data cache and instruction data cache |
124 | ![[Patents]](../gifs/ps.gif) | . . . . Cross-interrogating |
125 | ![[Patents]](../gifs/ps.gif) | . . . Instruction data cache |
126 | ![[Patents]](../gifs/ps.gif) | . . . User data cache |
127 | ![[Patents]](../gifs/ps.gif) | . . . Interleaved |
128 | ![[Patents]](../gifs/ps.gif) | . . . Associative |
129 | ![[Patents]](../gifs/ps.gif) | . . . Partitioned cache |
130 | ![[Patents]](../gifs/ps.gif) | . . . Shared cache |
131 | ![[Patents]](../gifs/ps.gif) | . . . Multiport cache |
132 | ![[Patents]](../gifs/ps.gif) | . . . Stack cache |
133 | ![[Patents]](../gifs/ps.gif) | . . . Entry replacement strategy |
134 | ![[Patents]](../gifs/ps.gif) | . . . . Combined replacement modes |
135 | ![[Patents]](../gifs/ps.gif) | . . . . Cache flushing |
136 | ![[Patents]](../gifs/ps.gif) | . . . . Least recently used |
137 | ![[Patents]](../gifs/ps.gif) | . . . Look-ahead |
138 | ![[Patents]](../gifs/ps.gif) | . . . Cache bypassing |
139 | ![[Patents]](../gifs/ps.gif) | . . . . No-cache flags |
140 | ![[Patents]](../gifs/ps.gif) | . . . Cache pipelining |
141 | ![[Patents]](../gifs/ps.gif) | . . . Coherency |
142 | ![[Patents]](../gifs/ps.gif) | . . . . Write-through |
143 | ![[Patents]](../gifs/ps.gif) | . . . . Write-back |
144 | ![[Patents]](../gifs/ps.gif) | . . . . Cache status data bit |
145 | ![[Patents]](../gifs/ps.gif) | . . . . Access control bit |
146 | ![[Patents]](../gifs/ps.gif) | . . . . Snooping |
147 | ![[Patents]](../gifs/ps.gif) | . Shared memory area |
148 | ![[Patents]](../gifs/ps.gif) | . . Plural shared memories |
149 | ![[Patents]](../gifs/ps.gif) | . . Multiport memory |
150 | ![[Patents]](../gifs/ps.gif) | . . Simultaneous access regulation |
151 | ![[Patents]](../gifs/ps.gif) | . . Prioritized access regulation |
152 | ![[Patents]](../gifs/ps.gif) | . . Memory access blocking |
153 | ![[Patents]](../gifs/ps.gif) | . . Shared memory partitioning |
154 | ![[Patents]](../gifs/ps.gif) | . Control technique |
155 | ![[Patents]](../gifs/ps.gif) | . . Read-modify-write (RMW) |
156 | ![[Patents]](../gifs/ps.gif) | . . Status storage |
157 | ![[Patents]](../gifs/ps.gif) | . . Interleaving |
158 | ![[Patents]](../gifs/ps.gif) | . . Prioritizing |
159 | ![[Patents]](../gifs/ps.gif) | . . Entry replacement strategy |
160 | ![[Patents]](../gifs/ps.gif) | . . . Least recently used (LRU) |
161 | ![[Patents]](../gifs/ps.gif) | . . Archiving |
162 | ![[Patents]](../gifs/ps.gif) | . . . Backup |
163 | ![[Patents]](../gifs/ps.gif) | . . Access limiting |
164 | ![[Patents]](../gifs/ps.gif) | . . . With password or key |
165 | ![[Patents]](../gifs/ps.gif) | . . Internal relocation |
166 | ![[Patents]](../gifs/ps.gif) | . . Resetting |
167 | ![[Patents]](../gifs/ps.gif) | . Access timing |
168 | ![[Patents]](../gifs/ps.gif) | . . Concurrent accessing |
169 | ![[Patents]](../gifs/ps.gif) | . . Memory access pipelining |
170 | ![[Patents]](../gifs/ps.gif) | . Memory configuring |
171 | ![[Patents]](../gifs/ps.gif) | . . Based on data size |
172 | ![[Patents]](../gifs/ps.gif) | . . Based on component size |
173 | ![[Patents]](../gifs/ps.gif) | . . Memory partitioning |
200 | ![[Patents]](../gifs/ps.gif) | ADDRESS FORMATION |
201 | ![[Patents]](../gifs/ps.gif) | . Slip control, misaligning, boundary alignment |
202 | ![[Patents]](../gifs/ps.gif) | . Address mapping (e.g., conversion, translation) |
203 | ![[Patents]](../gifs/ps.gif) | . . Virtual addressing |
204 | ![[Patents]](../gifs/ps.gif) | . . . Predicting, look-ahead |
205 | ![[Patents]](../gifs/ps.gif) | . . . . Directories and tables (e.g., DLAT, TLB) |
206 | ![[Patents]](../gifs/ps.gif) | . . . Translation tables (e.g., segment and page table or map) |
207 | ![[Patents]](../gifs/ps.gif) | . . . . Directory tables (e.g., DLAT, TLB) |
208 | ![[Patents]](../gifs/ps.gif) | . . . . Segment or page table descriptor |
209 | ![[Patents]](../gifs/ps.gif) | . . . Including plural logical address spaces, pages, segments, blocks |
210 | ![[Patents]](../gifs/ps.gif) | . . Resolving conflict, coherency, or synonym problem |
211 | ![[Patents]](../gifs/ps.gif) | . Address multiplexing or address bus manipulation |
212 | ![[Patents]](../gifs/ps.gif) | . Varying address bit-length or size |
213 | ![[Patents]](../gifs/ps.gif) | . Generating prefetch, look-ahead, jump, or predictive address |
214 | ![[Patents]](../gifs/ps.gif) | . Operand address generation |
215 | ![[Patents]](../gifs/ps.gif) | . In response to microinstruction |
216 | ![[Patents]](../gifs/ps.gif) | . Hashing |
217 | ![[Patents]](../gifs/ps.gif) | . Generating a particular pattern/sequence of addresses |
218 | ![[Patents]](../gifs/ps.gif) | . . Sequential addresses generation |
219 | ![[Patents]](../gifs/ps.gif) | . Incrementing, decrementing, or shifting circuitry |
220 | ![[Patents]](../gifs/ps.gif) | . Combining two or more values to create address |
221 | ![[Patents]](../gifs/ps.gif) | . Using table |