| US 7,471,548 B2 | ||
| Structure of static random access memory with stress engineering for stability | ||
| Christopher V. Baiocco, Newburgh, N.Y. (US); Xiangdong Chen, Poughquag, N.Y. (US); Young G. Ko, Fishkill, N.Y. (US); and Melanie J. Sherony, Fishkill, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US); and Samsung Electronics Co., Ltd., Gyeonggi-Do (Korea, Republic of) | ||
| Filed on Dec. 15, 2006, as Appl. No. 11/611,569. | ||
| Prior Publication US 2008/0142895 A1, Jun. 19, 2008 | ||
| Int. Cl. G11C 11/412 (2006.01); H01L 29/78 (2006.01) | ||
| U.S. Cl. 365—156 [365/154; 365/51; 365/72; 257/418; 257/903] | 1 Claim |
| 1. An integrated circuit (IC) comprising:
a first area containing at least one SRAM cell, wherein said at least one SRAM cell includes at least one nFET and at least
one pFET;
a second area containing at least one logic nFET and at least one logic pFET; and
a continuous stressed liner comprising a compressively stressed silicon nitride located above and adjoining each FET, wherein
a first portion of said continuous stressed liner located in said second area above and adjoining said at least one logic
nFET is relaxed and includes at least one of Xe ions and Ge ions, a second portion of said continuous stressed liner located
in said second area above and adjoining said at least one logic pFET is non-relaxed, and a third portion of said continuous
stressed liner located in said first area above and adjoining said at least one nFET and said at least one pFET is relaxed
and includes at least one of Xe ions and Ge ions.
|