| US 7,471,228 B2 | ||
| Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry | ||
| Taehee Cho, Irvine, Calif. (US); Sandor L. Barna, Pasadena, Calif. (US); Andrew M. Lever, Surrey (United Kingdom); Kwang-Bo Cho, Los Angeles, Calif. (US); and Chiajen Lee, Irvine, Calif. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Nov. 28, 2006, as Appl. No. 11/604,901. | ||
| Application 11/604901 is a continuation of application No. 11/211566, filed on Aug. 26, 2005, granted, now 7,148,833. | ||
| Prior Publication US 2007/0090987 A1, Apr. 26, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03M 1/42 (2006.01) | ||
| U.S. Cl. 341—162 [341/161; 348/308] | 16 Claims |
| 1. A method of operating a pipelined analog-to-digital converter comprising first and second stages sharing an amplifier,
said method comprises:
performing a first discharge operation at the amplifier in response to a first reset pulse during a first period in which
the first and second stages change operations, wherein the first period occurs after a first clock signal is used to cause
the first stage to perform a first operation and the second stage to perform a second operation, but before a second clock
signal is used to cause the first stage to perform the second operation and the second stage to perform the first operation;
and
performing a second discharge operation at the amplifier during a second period in which the first and second stages change
operations,
wherein the second period occurs after the second clock signal is used to cause the first stage to perform the second operation
and the second stage to perform the first operation.
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