| US 7,470,586 B2 | ||
| Memory cell having bar-shaped storage node contact plugs and methods of fabricating same | ||
| Jun-Shik Bae, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Nov. 13, 2007, as Appl. No. 11/939,472. | ||
| Application 11/939472 is a division of application No. 10/891806, filed on Jul. 14, 2004, granted, now 7,312,489. | ||
| Claims priority of application No. 2003-48082 (KR), filed on Jul. 14, 2003. | ||
| Prior Publication US 2008/0064161 A1, Mar. 13, 2008 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—250 [438/253; 438/258; 438/396; 438/618; 438/637; 257/E21.507; 257/E21.587; 257/E21.648; 257/E21.659] | 9 Claims |
| 1. A method of fabricating a DRAM cell comprising:
forming a bit line interlayer insulating layer over a semiconductor substrate;
forming parallel bit line patterns on the bit line interlayer insulating layer, each of the bit line patterns including a
bit line and a bit line capping layer pattern stacked thereon;
forming bit line spacers on sidewalls of the parallel bit line patterns;
selectively etching the bit line interlayer insulating layer between the parallel bit line patterns to form buried holes;
filling the buried holes with storage node contact plug patterns;
forming photoresist patterns on the semiconductor substrate having the storage node contact plug patterns, the photoresist
patterns disposed between the parallel bit line patterns; and
etching the storage node contact plug patterns by using photoresist patterns, the bit line patterns, the bit line spacers,
and the bit line interlayer insulating layer as an etching mask to form storage node contact plugs.
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