	US 7,469,357 B2
	Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control
Christopher Michael Abernathy, Austin, Tex. (US); Gilles Gervais, Austin, Tex. (US); and Rolf Hilgendork, Boeblingen (Germany)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Oct. 25, 2006, as Appl. No. 11/552,790.
Application 11/552790 is a continuation of application No. 10/042082, filed on Jan. 07, 2002, granted, now 7,137,013.
Prior Publication US 2007/0050652 A1, Mar. 01, 2007
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/04 (2006.01)

U.S. Cl. 713—600 [713/300; 713/601]

6 Claims

1. A method for dynamically reducing power consumption in a microprocessor configured for executing at least an instruction, the microprocessor having a main processor clock, the method comprising the steps of:

storing operand data in a first stage of one or more storage components residing in the microprocessor, the first stage being clocked by at least a first clock derived from the main processor clock;

transmitting the operand data from the first stage to a first combinatorial logic residing in the microprocessor, wherein the first clock is operational only during a first period of time when the operand data is processed by the first combinatorial logic;

processing the operand data in the first combinatorial logic;

generating first output data from the first combinatorial logic;

storing the first output data in a second stage of one or more storage components residing in the microprocessor, the second stage being clocked by at least a second clock derived from the main processor clock;

transmitting the first output data from the second stage to a second combinatorial logic residing in the microprocessor, wherein the second clock is operational only during a second period of time when the first output data is processed by the second combinatorial logic;

processing the first output data in the second combinatorial logic;

generating second output data from the second combinatorial logic;

generating at least two instruction-valid control bits;

in response to the instruction-valid control bits, reducing power consumption in the microprocessor by dynamically controlling the first and second clocks by selectively disabling at least one local clock buffer to prevent switching of the first clock or the second clock;

generating a scan mode signal, wherein in response to the scan mode signal, the instruction-valid control bits enable the first clock and the second clock; and

disabling the first clock by a first instruction-valid control bit in response to a first stop control signal and disabling the second clock by a second instruction-valid control bit in response to a second stop control signal.