US 7,469,328 B1
Synchronization technique for high speed memory subsystem
Kwok Ken Mak, Chapel Hill, N.C. (US); and Xiaoming Sun, Chapel Hill, N.C. (US)
Assigned to Cisco Technology, Inc., San Jose, Calif. (US)
Filed on Feb. 06, 2003, as Appl. No. 10/359,985.
Int. Cl. G06F 13/28 (2006.01); G06F 12/12 (2006.01)
U.S. Cl. 711—167  [711/159] 29 Claims
OG exemplary drawing
 
1. A method for synchronizing data retrieved from memory devices of a memory subsystem in an intermediate network node, each memory device organized into a plurality of data groupings, the method comprising the steps of:
writing, by a memory controller, data including a synchronization (sync) pattern over a memory bus to each data grouping on the memory devices, the memory bus directly connecting the memory controller to the memory devices;
providing synchronization logic at the memory controller for each data grouping;
retrieving the sync pattern over the memory bus from each data grouping for storage at an associated synchronization logic of the memory controller;
comparing the retrieved sync pattern at the synchronization logic with a local sync pattern stored in a comparator within the synchronization logic; and
automatically, in response to the retrieved sync pattern and the local sync pattern matching, synchronizing data retrieved from the data groupings on the memory devices each time the data is retrieved from the data groupings, to compensate for skew between data retrieved from different data groupings.