| US 7,469,304 B2 | ||
| Data transfer control device, electronic equipment, and method for a data transfer through a bus, the data transfer control device including a register and a packet buffer that are commonly used during a host operation and a peripheral operation | ||
| Nobuyuki Saito, Sapporo (Japan); Hiroaki Shimono, Sapporo (Japan); Yoshiyuki Kamihara, Sapporo (Japan); and Hironobu Kazama, Sapporo (Japan) | ||
| Assigned to Seiko Epson Corporation, Tokyo (Japan) | ||
| Filed on Feb. 21, 2003, as Appl. No. 10/369,630. | ||
| Claims priority of application No. 2002-118251 (JP), filed on Apr. 19, 2002. | ||
| Prior Publication US 2003/0200360 A1, Oct. 23, 2003 | ||
| Int. Cl. G06F 3/00 (2006.01) | ||
| U.S. Cl. 710—7 [710/5; 710/36; 710/52] | 21 Claims |
| 1. A data transfer control device for data transfer through a bus, comprising:
a state controller which controls a plurality of states including a state of a host operation, in which the data transfer
control device operates as a role of a host, and a state of a peripheral operation, in which the data transfer control device
operates as a role of a peripheral;
a host controller which is connected with a transceiver including a physical layer circuit during the host operation and transfers
data as the host;
a peripheral controller which is connected with the transceiver during the peripheral operation and transfers data as the
peripheral;
a register section including a common register which is used commonly during the host operation and the peripheral operation;
and
a buffer controller which controls access to a packet buffer which stores data transferred by the host controller and the
peripheral controller and is used commonly by the host controller and the peripheral controller,
the packet buffer being a local memory of the data transfer control device,
during the host operation, a plurality of pipe regions being allocated in the packet buffer and the host controller transferring
data between the plurality of pipe regions and a plurality of endpoints, each of the plurality of pipe regions storing data
transferred to and from corresponding each of the plurality of endpoints,
the plurality of the pipe regions including a pipe region for an endpoint of control transfer and other pipe regions, and
the plurality of the pipe regions being allocated in the packet buffer simultaneously by an instruction from a processing
unit, and region calculation of the plurality of the pipe regions based on the instruction,
during the peripheral operation, a plurality of endpoint regions being allocated in the packet buffer and the peripheral controller
transfers data between the plurality of endpoint regions and the host, each of the plurality of endpoint regions storing data
transferred to and from the host,
the plurality of the endpoint regions including an endpoint region for control transfer and other endpoint regions, and the
plurality of the endpoint regions being allocated in the packet buffer simultaneously by an instruction from the processing
unit, and region calculation of the plurality of the endpoint regions being based on the instruction,
an access address of the common register being set to be the same and the same information content being set in the area of
the common register specified by the same access address both during the host operation and the peripheral operation,
the processing unit accessing the common register by using the same access address and setting the same information content
to the area of the common register specified by the same access address both during the host operation and the peripheral
operation.
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