| US 7,469,273 B2 | ||
| Multi-processor system verification circuitry | ||
| Marquette John Anderson, Cagnes sur Mer (France); and Hakim Bederr, Villeneuve-Loubet (France) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Feb. 07, 2001, as Appl. No. 9/778,495. | ||
| Claims priority of application No. 00401957 (EP), filed on Jul. 06, 2000. | ||
| Prior Publication US 2002/0004823 A1, Jan. 10, 2002 | ||
| Int. Cl. G06F 15/173 (2006.01) | ||
| U.S. Cl. 709—213 [709/245; 709/208; 709/215; 710/100; 710/305; 711/100; 711/147; 711/148; 711/150; 711/152] | 15 Claims |
| 1. A processing device comprising:
a master processor;
a system memory;
a slave processor subsystem including:
a slave processor;
a shared memory accessible by said master processor and said slave processor;
an external memory interface allowing said slave processor to access said system memory;
circuitry for receiving a signal for specifying a normal mode for normal operation of the processing device or verification
mode for testing the processing device; and
a verification interface for selectively passing system memory accesses either to the system memory or the shared memory responsive
to the signal, wherein accesses directed towards the system memory access are passed to said system memory in a normal mode
and wherein accesses directed towards the system memory are passed to said shared memory in a verification mode.
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