| US 7,469,057 B2 | ||
| System and method for inspecting errors on a wafer | ||
| Chang-Cheng Hung, Hsin-chu (Taiwan); Hung-Chang Hsieh, Hsinchu (Taiwan); Hsen-Lin Wu, Hsin-chu (Taiwan); and Tyng-Hao Hsu, Hsin-chu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Corp, Hsin-Chu, Taiwan (China) | ||
| Filed on Feb. 18, 2004, as Appl. No. 10/781,107. | ||
| Claims priority of provisional application 60/450177, filed on Feb. 26, 2003. | ||
| Prior Publication US 2004/0165761 A1, Aug. 26, 2004 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06K 9/00 (2006.01) | ||
| U.S. Cl. 382—144 [324/750; 382/149; 382/218; 716/19] | 20 Claims |
| 1. A method for inspecting defects in a wafer, the method comprising:
acquiring at least one digitized image of at least one actual feature on the wafer taken directly from the wafer;
converting at least one design database file corresponding to the feature of the wafer into at least one inspection file;
setting one or more error detection thresholds;
comparing the digitized image and the inspection file by an inspection tool for detecting defects with regard to the feature
of the wafer based on the set error detection thresholds; and
selectively applying bias parameters to one of either the digitized image or inspection file when false defects are detected
at a post process review station between the digitized image and inspection file.
|