| US 7,469,028 B2 | ||
| Asymmetrical digital subscriber line system | ||
| Jun-Young Jeong, Suwon-shi (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Feb. 02, 2004, as Appl. No. 10/770,327. | ||
| Claims priority of application No. 10-2003-0009158 (KR), filed on Feb. 13, 2003. | ||
| Prior Publication US 2004/0161081 A1, Aug. 19, 2004 | ||
| Int. Cl. H04L 7/00 (2006.01); H04L 27/28 (2006.01) | ||
| U.S. Cl. 375—355 [375/260] | 8 Claims |

| 1. A digital communication system using telephone lines, comprising:
an analog-to-digital converter that generates a time-domain digital signal comprising frames from an analog signal received
through the telephone line in response to a sampling clock signal;
a converter that transforms the time-domain digital signal to frequency-domain digital signals;
a frequency equalizer that conducts a frequency equalization of the frequency-domain digital signals;
a selector that selects a digital signal of the frequency-equalized digital signals, wherein the selected digital signal has
the highest signal-to-noise ratio (SNR) among the digital signals;
an operation block that receives the selected digital signal having the highest SNR from the selector, and generates a selected
highest SNR digital signal set at a constant position by performing an operation every frame on a constellation value of the
selected digital signal having the highest SNR and a coefficient corresponding to the constellation value of the selected
digital signal having the highest SNR to set the selected digital signal having the highest SNR at the constant position,
wherein the operation block modifies the coefficient to generate a modified coefficient corresponding to the constellation
value of the selected digital signal having the highest SNR every frame; and
a loop circuit that receives from the operation block the selected highest SNR digital signal set at the constant position
and conducts a PLL operation using the selected digital signal having the highest SNR set at the constant position as a reference
signal to generate the sampling clock signal to be applied to the analog-to-digital converter.
|