	US 7,468,991 B2
	Methods and devices for synchronizing the timing of logic cards in a packet switching system without data loss
Frank Bradbury, Saugus, Mass. (US); John Patrick Jones, Westford, Mass. (US); Douglas MacIntyre, Berlin, Mass. (US); Raymond Schmidt, Stoughton, Mass. (US); and Scott Whitney, Chelmsford, Mass. (US)
Assigned to Alcatel-Lucent USA Inc., Murray Hill, N.J. (US)
Filed on Mar. 17, 2003, as Appl. No. 10/388,438.
Prior Publication US 2004/0184485 A1, Sep. 23, 2004
Int. Cl. H04J 3/06 (2006.01)

U.S. Cl. 370—503 [375/357]

11 Claims

1. A synchronous timing circuit comprising:

a first clock circuit for generating a reference frequency based on a first oscillation signal or second oscillation signal, the first circuit comprising a first oscillator for generating the first oscillation signal, a first reference frequency selection section for selecting the first or second oscillation signal and a first delay section for adding a first delay to the first oscillation signal when necessary; and

a second clock circuit for generating substantially the same reference frequency based on the first or second oscillation signal, the second circuit comprising a second oscillator for generating the second oscillation signal, a second reference frequency selection section for selecting the first or second oscillation signal and a second delay section for adding a second delay to the second oscillation signal when necessary.