| US 7,468,926 B2 | ||
| Partial erase verify | ||
| Assaf Shappir, Kiryat Ono (Israel); and Shai Eisen, Tel Aviv (Israel) | ||
| Assigned to Saifun Semiconductors Ltd., Netanya (Israel) | ||
| Filed on Jan. 19, 2006, as Appl. No. 11/335,321. | ||
| Claims priority of provisional application 60/644569, filed on Jan. 19, 2005. | ||
| Prior Publication US 2006/0158940 A1, Jul. 20, 2006 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—218 [365/185.19; 365/200] | 11 Claims |
| 1. A method for erasing memory cells in a memory array, the method comprising: applying an erase pulse to bits of a cell ensemble of a memory cell array; and designating the entire cell ensemble as erase verified once an erase verification operation on a subgroup of the cell ensemble being erased indicates a memory cell threshold voltage (Vt) of each cell in the subgroup has reached an erase verify (EV) voltage level. |