US 7,468,915 B2
Method of reducing disturbs in non-volatile memory
Daniel C. Guterman, Fremont, Calif. (US); George Samachisa, San Jose, Calif. (US); Brian Murphy, San Jose, Calif. (US); Chi-Ming Wang, Fremont, Calif. (US); and Khandker N. Quader, Sunnyvale, Calif. (US)
Assigned to SanDisk Corporation, Milpitas, Calif. (US)
Filed on Oct. 04, 2006, as Appl. No. 11/538,521.
Application 11/054084 is a division of application No. 10/613098, filed on Jul. 01, 2003, granted, now 6,888,752.
Application 10/613098 is a division of application No. 09/759835, filed on Jan. 10, 2001, granted, now 6,717,851.
Application 11/538521 is a continuation of application No. 11/238911, filed on Sep. 28, 2005, granted, now 7,145,804.
Application 11/238911 is a continuation of application No. 11/054084, filed on Feb. 08, 2005, granted, now 6,977,844.
Application 09/759835 is a continuation in part of application No. 09/703083, filed on Oct. 31, 2000, granted, now 6,570,785.
Prior Publication US 2007/0076510 A1, Apr. 05, 2007
Int. Cl. G11C 11/34 (2006.01)
U.S. Cl. 365—185.23  [365/230.06] 7 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
a plurality of word lines;
a plurality of bit lines;
a plurality of non-volatile memory cells each connected to a corresponding bit line and a corresponding word line, wherein information is stored in a selected one of the memory cells by applying a first voltage to the corresponding word line to which the selected cell is connected and a second voltage to the corresponding bit line to which the selected cell is connected;
a switch whereby the second voltage is provided to the bit line corresponding to the selected cell; and
a voltage generator circuit connected to received a program enable signal and provide to the switch for the control thereof a voltage gated by the leading edge of the program enable signal, whereby the ramp rate of the second voltage is controlled by the ramp rate of the voltage gated by the leading edge of the program enable signal.