| US 7,468,908 B2 | ||
| Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell | ||
| Tomoharu Tanaka, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 30, 2007, as Appl. No. 11/929,152. | ||
| Application 11/929152 is a continuation of application No. 10/871110, filed on Jun. 21, 2004, granted, now 7,301,806. | ||
| Claims priority of application No. 2003-410237 (JP), filed on Dec. 09, 2003. | ||
| Prior Publication US 2008/0068893 A1, Mar. 20, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—185.03 [365/185.18; 365/185.33; 365/185.24; 365/185.22; 365/185.19] | 5 Claims |
| 1. A non-volatile semiconductor memory device comprising:
an electrically data rewritable non-volatile semiconductor memory cell; and
a write circuit configured to write data to the memory cell by supplying a write voltage and a write control voltage to the
memory cell to change the write state of the memory cell, the write circuit detecting if the write state of the memory cell
has reached a first level or not and, upon detecting that the write state of the memory cell has reached the first level,
the write circuit reducing a rate of change of the write state by changing the supply of the write control voltage,
wherein the write circuit performs a write operation to sequentially increase the write voltage when writing data to the memory
cell,
the write circuit controls the rate of change of the reduced rate of change of the write state by sequentially increasing
the write control voltage, and
the rate of increase of the write voltage is greater than the rate of increase of the write control voltage.
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