| US 7,468,907 B2 | ||
| Programming method for flash memory capable of compensating reduction of read margin between states due to hot temperature stress | ||
| Dong-Ku Kang, Seongnam-si (Korea, Republic of); and Young-Ho Lim, Yongin-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Sep. 18, 2006, as Appl. No. 11/522,406. | ||
| Claims priority of application No. 10-2006-003584 (KR), filed on Jan. 12, 2006. | ||
| Prior Publication US 2007/0159889 A1, Jul. 12, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.03 [365/185.22; 365/185.24] | 17 Claims |
| 1. A programming method for a flash memory device having a plurality of memory cells storing multi-bit data indicating one
of a plurality of states, the programming method comprising:
programming memory cells selected to have one of the plurality of states using multi-bit data;
detecting programmed memory cells within a predetermined region of a threshold voltage distribution, wherein the programmed
memory cells have one of the plurality of states,
wherein the predetermined region is selected by one of a first verify voltage and a read voltage and a second verify voltage,
the first verify voltage being lower than the second verify voltage and higher than the read voltage; and
programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage
corresponding to the respective states.
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