| US 7,468,906 B2 | ||
| Word driver and decode design methodology in MRAM circuit | ||
| Chien-Teh Kuo, St. Paul, Minn. (US); and James Chyi Lai, St. Paul, Minn. (US) | ||
| Assigned to Northern Lights Semiconductor Corp., St. Paul, Minn. (US) | ||
| Filed on Sep. 11, 2006, as Appl. No. 11/530,704. | ||
| Claims priority of provisional application 60/716714, filed on Sep. 13, 2005. | ||
| Prior Publication US 2007/0070688 A1, Mar. 29, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—158 [365/46; 365/55; 365/74; 365/97; 365/173] | 20 Claims |
| 1. A magnetic random access memory with word line driver and decode apparatus, comprising:
a plurality of memory segment;
a plurality of word lines, disposed on the memory segments, being capable of providing an electric field for reading and writing
data on the magnetic random access memory;
a main word line driver connected to first terminals of the word lines and providing a reading current for read operation
of the word lines and a writing current for write operation of the word lines, wherein the main word line driver further comprises
a logic control circuit determining the read operation and the write operation of the word lines;
a plurality of multiplexers connected to second terminals, opposite to the first terminals, of the respective word lines and
capable of controlling directions of the reading current and the writing current on the word lines; and
a sub word line driver connected to the multiplexers by a mux control bus and capable of choosing a required multiplexer from
the multiplexers to be active to process one of the word lines;
wherein the main word line driver, the multiplexers and the sub word line driver together decode addresses and perform the
read and write operations to read and write data on the magnetic random access memory.
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