US 7,468,904 B2
Apparatus for hardening a static random access memory cell from single event upsets
David C. Lawson, Haymarket, Va. (US); and Jason Ross, Fairfax, Va. (US)
Assigned to BAE Systems Information and Electronic Systems Integration Inc., Nashua, N.H. (US)
Filed on Feb. 23, 2007, as Appl. No. 11/678,097.
Prior Publication US 2008/0205112 A1, Aug. 28, 2008
Int. Cl. G11C 11/00 (2006.01)
U.S. Cl. 365—154  [365/148; 365/149] 20 Claims
OG exemplary drawing
 
1. A single event upset hardened memory cell comprising:
a first inverter and a second inverter connected to each other in a cross-coupled manner;
a first resistor connected between an input of said first inverter and an output of said second inverter;
a second resistor connected between an input of said second inverter and an output of said first inverter; and
a capacitor connected between an input of said first inverter and an input of said second inverter.