| US 7,468,903 B2 | ||
| Circuits for improving read and write margins in multi-port SRAMS | ||
| Dao-Ping Wang, Hsinchu (Taiwan); Hung-Jen Liao, Hsinchu (Taiwan); Kun Lung Chen, Taipei (Taiwan); Yung-Lung Lin, Taichung (Taiwan); Jui-Jen Wu, Hsinchu (Taiwan); and Chen Yen-Huei, Hsinchu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Nov. 13, 2006, as Appl. No. 11/598,385. | ||
| Prior Publication US 2008/0112212 A1, May 15, 2008 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—154 [365/202] | 17 Claims |
| 1. A method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs), the method comprising:
asserting a word-line (WL) selecting the SRAM cell to a first positive voltage;
providing a second positive voltage at the first BL;
providing a first negative voltage at the second BL; and
asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the asserting the second negative
voltage further comprises providing a third negative voltage at a source and bulk of a NMOS transistor with a drain coupled
to one of the plurality of WLs, and
wherein the writing margin of the SRAM cell is increased.
|