| US 7,468,902 B2 | ||
| SRAM device with a low operation voltage | ||
| Jhon Jhy Liaw, Hsin-Chu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Sep. 27, 2006, as Appl. No. 11/527,965. | ||
| Prior Publication US 2008/0074916 A1, Mar. 27, 2008 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—154 [365/189.01; 365/185.14] | 17 Claims |
| 1. A static random access memory (SRAM) cell comprising:
a first PMOS transistor having a source coupled to a supply voltage;
a second PMOS transistor having a source coupled to the supply voltage, a drain coupled to a gate of the first PMOS transistor,
and a gate coupled to a drain of the first PMOS transistor;
a first write switch module coupled between the first PMOS transistor and a complementary supply voltage, wherein the first
write switch module comprises a first NMOS transistor and a second NMOS transistor serially coupled between the drain of the
first PMOS transistor and the complementary supply voltage, the first NMOS transistor having a gate being controlled by a
write bit line; and the second NMOS transistor having a gate being controlled by a write word line;
a second write switch module coupled between the second PMOS transistor and the complementary supply voltage; and
a read switch module coupled between the gate of the first PMOS transistor and a read bit line,
wherein the first write switch module, the second write switch module, and the read switch module are controlled separately
to write or read a logic value to or from one or more storage nodes at the drains of the first and second PMOS transistors.
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