| US 7,468,901 B2 | ||
| Semiconductor memory device | ||
| Norifumi Kameshiro, Kokubunji (Japan); Riichiro Takemura, Tokyo (Japan); and Tomoyuki Ishii, Kokubunji (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Apr. 07, 2006, as Appl. No. 11/399,397. | ||
| Claims priority of application No. 2005-112495 (JP), filed on Apr. 08, 2005. | ||
| Prior Publication US 2006/0227648 A1, Oct. 12, 2006 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—149 [365/230.05] | 17 Claims |
| 1. A semiconductor memory device comprising a memory cell array including memory cells arranged in a matrix shape, the memory
cells being divided into memory cell pairs, each of which consists of two memory cells adjacent each other,
wherein each memory cell pair includes a first write transistor, a first read transistor, a second write transistor, and a
second read transistor,
wherein the first read transistor and the first write transistor constitute parts of a first memory cell and the second read
transistor and the second write transistor constitute parts of a second memory cell,
wherein a gate electrode of the first read transistor is connected to one of a source and a drain of the first write transistor,
wherein a gate electrode of the second read transistor is connected to one of a source and a drain of the second write transistor,
wherein one of a source and a drain of the first read transistor, and one of a source and a drain of the second read transistor
are connected to a read word line, and
wherein the other of the source and the drain of the first write transistor, and the other of the source and the drain of
the second write transistor are connected to a write bit line.
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