US 7,468,900 B2
Semiconductor memory device having a bitline amplified to a positive voltage and a negative voltage
Kunisato Yamaoka, Osaka (Japan); Hiroshige Hirano, Nara (Japan); and Masahiko Sakagami, Kyoto (Japan)
Assigned to Panasonic Corporation, Osaka (Japan)
Filed on Feb. 17, 2006, as Appl. No. 11/356,213.
Claims priority of application No. 2005-180198 (JP), filed on Jun. 21, 2005.
Prior Publication US 2006/0285378 A1, Dec. 21, 2006
Int. Cl. G11C 11/22 (2006.01)
U.S. Cl. 365—145  [365/208; 365/189.09; 365/203; 365/149] 22 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising a memory cell composed of a transistor and a capacitor, and in which a word line is connected to a gate of the transistor, a bit line is connected to a drain of the transistor, a first electrode of the capacitor is connected to a source of the transistor, a cell plate line is connected to a second electrode of the capacitor, and the memory cell is placed at an intersection between the word line and the bit line,
wherein the cell plate line is fixed to a potential substantially equal to a ground potential and the bit line is amplified to a positive voltage and a negative voltage to read a potential difference between the positive voltage and the cell plate line or a potential difference between the negative voltage and the cell plate line.