| US 7,468,750 B2 | ||
| Solid state imaging device having transition time relationship for drive signals | ||
| Keiji Mabuchi, Kanagawa (Japan); Eiichi Funatsu, Tokyo (Japan); and Masanori Kasai, Kanagawa (Japan) | ||
| Assigned to Sony Corporation, Tokyo (Japan) | ||
| Filed on Apr. 16, 2004, as Appl. No. 10/826,038. | ||
| Claims priority of application No. 2003-113840 (JP), filed on Apr. 18, 2003. | ||
| Prior Publication US 2005/0001915 A1, Jan. 06, 2005 | ||
| Int. Cl. H04N 3/14 (2006.01); H04N 5/335 (2006.01); H01L 27/00 (2006.01) | ||
| U.S. Cl. 348—308 [348/310; 348/297; 250/208.1] | 16 Claims |
| 1. A solid-state imaging device comprising:
unit pixels including:
a charge generating section for generating a charge in an amount corresponding to a light received,
a charge storing part for storing a charge generated by the charge generating section,
a transfer gate section arranged between the charge generating section and the charge storing part for transferring the signal
charge generated by the charge generating section to the charge storing part,
a pixel signal generating section for generating a pixel signal corresponding to the signal charge stored in the charge storing
part, and
a reset section for resetting a level of the charge storing part;
a transfer line connected commonly with other unit pixels and connected to the transfer gate section;
a transfer drive buffer for driving the transfer line;
a reset line connected commonly with other unit pixels and connected to the reset section;
a reset drive buffer for driving the reset line;
a drain line connected commonly with other unit pixels and connected to the reset section and the pixel signal generating
section;
a drain drive buffer for driving the drain line; and
a signal line for receiving the pixel signal generated by the pixel signal generating section and connected commonly with
other unit pixels;
whereby a pixel select operation, for outputting the pixel signal generated by the pixel signal generating section to the
signal line, is carried out under potential control at the charge storing part; and
wherein an off transition time of a voltage waveform on the drain line when driven by the drain drive buffer, is five times
or greater and ten thousand times or smaller relative to an off transition time on any of the signals applied to the reset
line when driven by the reset drive buffer and the transfer line when driven by the transfer driven buffer.
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