US 7,468,685 B1
Clockless serialization using delay circuits
Steven M. Macaluso, Scarborough, Me. (US)
Assigned to Fairchild Semiconductor Corporation, South Portland, Me. (US)
Filed on Aug. 20, 2007, as Appl. No. 11/841,237.
Int. Cl. H03M 9/00 (2006.01)
U.S. Cl. 341—101  [327/408] 14 Claims
OG exemplary drawing
 
1. A serializer comprising:
a series of one shot circuits functionally connected so that each one shot triggers the succeeding one shot; each one shot defining an enable output,
a first series of pass gates, each with an input coupled to a data bit, and each coupled to a first common output; and each of the first series of pass gates has an enable input coupled to a corresponding one shot output, wherein the data bit coupled to the pass gate input is transferred to the output when the enable is true;
a second series of pass gates, each with an input tied to a logic level, and each coupled to a second common output; wherein the logic level input of each succeeding pass gate alternates between a logic high and a logic low, and each of the second series of pass gates has an enable input coupled to a corresponding one shot output, wherein the logic level coupled to the pass gate input is transferred to the output when the enable is true; and wherein when the first one shot is activated, a series of signal edges occur at the second common output and simultaneously a series of data bits are transferred to the first common output.