| US 7,468,627 B2 | ||
| Multiple circuit blocks with interblock control and power conservation | ||
| Tadashi Hoshi, Higashimurayama (Japan); Kenji Hirose, Tokorozawa (Japan); Hideaki Abe, Higashiyamato (Japan); Junichi Nishimoto, Hachioji (Japan); and Midori Nagayama, Kodaira (Japan) | ||
| Assigned to Renesas Technology Corporation, Tokyo (Japan) | ||
| Filed on Jun. 08, 2006, as Appl. No. 11/448,743. | ||
| Application 11/015649 is a division of application No. 10/633567, filed on Aug. 05, 2003, granted, now 6,853,239, filed on Feb. 08, 2005. | ||
| Application 11/448743 is a continuation of application No. 11/015649, filed on Dec. 20, 2004, granted, now 7,078,959, filed on Jul. 18, 2006. | ||
| Application 10/633567 is a continuation of application No. 10/081186, filed on Feb. 25, 2002, granted, now 6,639,454, filed on Oct. 28, 2003. | ||
| Claims priority of application No. 2001-284383 (JP), filed on Sep. 19, 2001. | ||
| Prior Publication US 2006/0226895 A1, Oct. 12, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 327—545 [327/594; 365/229] | 4 Claims |
| 1. A data processor built in a semiconductor chip, comprising:
a first means for including a central processing unit;
a second means for including a base band processing unit and an I/O unit inputting or outputting a plurality of signals to
or from outside of said data processor;
a first voltage line coupled to said first means;
a second voltage line coupled to said second means; and
a control means,
wherein said data processor has a plurality of operation modes including an operation mode and a standby mode,
wherein said first means is supplied with a first operational level voltage from said first voltage line in said operation
mode, is not supplied with said operational level voltage in said standby mode,
wherein said second means is supplied with a second operational level voltage in said operation mode and standby modes,
wherein said first means couples to said second means via a data signal line and a memory unit,
wherein said control means controls said memory unit to provide a signal from said first means to said second means in said
operation mode,
wherein said control means controls said memory unit to store the signal from said first means before said operation mode
is changed to said standby mode, and
wherein said base band processing unit is capable of outputting a signal to outside of said data processor via said I/O unit
in said standby mode.
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