| US 7,468,626 B2 | ||
| Multiple circuit blocks with interblock control and power conservation | ||
| Tadashi Hoshi, Higashimurayama (Japan); Kenji Hirose, Tokorozawa (Japan); Hideaki Abe, Higashiyamato (Japan); Junichi Nishimoto, Hachioji (Japan); and Midori Nagayama, Kodaira (Japan) | ||
| Assigned to Renesas Technology Corporation, Tokyo (Japan) | ||
| Filed on Jun. 08, 2006, as Appl. No. 11/448,739. | ||
| Application 11/015649 is a division of application No. 10/633567, filed on Aug. 05, 2003, granted, now 6,853,239. | ||
| Application 11/448739 is a continuation of application No. 11/015649, filed on Dec. 20, 2004, granted, now 7,078,959. | ||
| Application 10/633567 is a continuation of application No. 10/081186, filed on Feb. 25, 2002, granted, now 6,639,454. | ||
| Claims priority of application No. 2001-284383 (JP), filed on Sep. 19, 2001. | ||
| Prior Publication US 2006/0226894 A1, Oct. 12, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 327—545 [327/594; 365/229] | 6 Claims |
| 1. A data processor built in a single semiconductor chip, comprising:
a first means for including a CPU;
a second means for including an I/O unit which inputs or outputs a plurality of signals to or from outside of said data processor;
a first voltage line coupled to said first means;
a second voltage line coupled to said second means; and
a control means,
wherein said first means is supplied with a first operational voltage from said first voltage line in an active mode, is not
supplied with said first operational voltage in a standby mode,
wherein said first means couples to said second means via a data signal line and a switching unit,
wherein said control means controls said switching unit to turn on in said active mode, and controls said switching unit to
turn off in said standby mode, and
wherein said data processor further comprises a memory which is arrayed between said switching unit and said second means.
|