US 7,468,621 B2
Synchronization circuits and methods
Jae-Hyuck Woo, Osan-si (Korea, Republic of); and Jae-Goo Lee, Suwon-si (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (Korea, Republic of)
Filed on May 26, 2006, as Appl. No. 11/441,610.
Claims priority of application No. 10-2005-0051120 (KR), filed on Jun. 14, 2005.
Prior Publication US 2006/0279348 A1, Dec. 14, 2006
Int. Cl. H03K 3/00 (2006.01)
U.S. Cl. 327—291  [327/292] 27 Claims
OG exemplary drawing
 
1. A synchronization circuit comprising:
a first level-shifting unit receiving an input reference signal having a first swing voltage and generating a first level change signal having a second swing voltage and a second level change signal having a third swing voltage, wherein peak-to-peak voltage of the first swing voltage is smaller than peak-to-peak voltage of one of the second and third swing voltages; and
a synchronization unit generating first and second output signals by buffering and level shifting the first and second level change signals, wherein the first and second output signals have substantially the same phase.