a comparator with a plurality of input nodes and at least one output node;

a parameter multiplexer with a plurality of input nodes and a selection input node, and an output node that is coupled to a first input node of the comparator;

a plurality of parameter multiplexer selection registers that are configurable to contain microcode-initialized values that are selectively coupled to the selection node of the parameter multiplexer so as to select an appropriate parameter multiplexer input node for application onto the parameter multiplexer output node, the plurality of parameter multiplexer selection registers including a selection input node for selecting one of the plurality of parameter multiplexer selection registers at a time for driving the selection node of the multiplexer;

a plurality of comparison threshold registers that are configurable to contain microcode-initialized values that are selectively coupled to a second input node of the comparator so as to provide comparison threshold data to the comparator, the plurality of comparison threshold registers also including the selection input node which also selects at least one of the plurality of comparison threshold registers at a time for providing to a second input node of the comparator;

at least one output retrieval register coupled to the output node of the comparator so as to hold a result of the comparison by the comparator during operation for later retrieval; and

a digital to analog converter having an input node and an output node interposed between the plurality of comparison threshold registers and the comparator,

wherein the plurality of comparison threshold registers are selectively coupled to the input node of the analog to digital converter and the output node of the digital to analog converter is coupled to the second input node of the comparator, the digital to analog converter for converting digital threshold data into analog data for use by the comparator.