| US 7,468,614 B2 | ||
| Configurable integrated circuit with offset connections | ||
| Andre Rohe, Mountain View, Calif. (US); and Steven Teig, Menlo Park, Calif. (US) | ||
| Assigned to Tabula, Inc., Santa Clara, Calif. (US) | ||
| Filed on Feb. 15, 2007, as Appl. No. 11/675,620. | ||
| Application 11/675620 is a continuation of application No. 10/882713, filed on Jun. 30, 2004, granted, now 7,193,438. | ||
| Prior Publication US 2007/0241789 A1, Oct. 18, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 25/00 (2006.01) | ||
| U.S. Cl. 326—41 [326/47; 326/101] | 20 Claims |
| 1. An integrated circuit (“IC”) comprising:
a set of at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and
a plurality of direct offset connections, wherein each particular direct offset connection connects two offset nodes that
are neither in the same column nor in the same row in the array, wherein at least one direct offset connection of said plurality
of direct offset connections comprises an intervening buffer circuit but does not comprise an intervening routing circuit,
and wherein said intervening buffer circuit is not inside either of said two offset nodes.
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