| US 7,468,544 B2 | ||
| Structure and process for WL-CSP with metal cover | ||
| Wen-Kun Yang, Hsin-Chu (Taiwan) | ||
| Assigned to Advanced Chip Engineering Technology Inc., Hsinchu County (Taiwan) | ||
| Filed on Dec. 07, 2006, as Appl. No. 11/567,795. | ||
| Prior Publication US 2008/0136026 A1, Jun. 12, 2008 | ||
| Int. Cl. H01L 23/544 (2006.01); H01L 23/48 (2006.01) | ||
| U.S. Cl. 257—620 [257/773; 257/786; 257/E21.599] | 19 Claims |
| 1. A wafer level package, comprising:
a wafer having a plurality of dice formed thereon, wherein said wafer has a trench formed therein, and said wafer is attached
on a metal cover layer by an adhesive material;
a dielectric layer formed over said plurality of dice and refilled into said trench to expose pads of said plurality of dice;
a protection film formed on back side of said metal cover layer;
a conductive trace formed on said dielectric layer and connected to said pads;
a solder mask covered on said conductive trace and said dielectric layer to expose a portion of said conductive trace; and
solder balls formed on said exposed portion and connected to said conductive trace.
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