| US 7,468,540 B2 | ||
| Semiconductor device and method for manufacturing the same | ||
| Tokuhiko Tamaki, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Jul. 06, 2006, as Appl. No. 11/480,902. | ||
| Claims priority of application No. 2005-293234 (JP), filed on Oct. 06, 2005. | ||
| Prior Publication US 2007/0080373 A1, Apr. 12, 2007 | ||
| Int. Cl. H01L 31/113 (2006.01); H01L 21/8234 (2006.01) | ||
| U.S. Cl. 257—401 [438/275] | 11 Claims |
| 1. A semiconductor device, comprising:
a first MIS transistor which is driven at a relatively low source voltage; and
a second MIS transistor which is driven at a relatively high source voltage, the first MIS transistor and the second MIS transistor
being formed on the same semiconductor substrate,
wherein the first MIS transistor includes:
a first gate insulating film formed on the semiconductor substrate;
a first gate electrode formed on the first gate insulating film;
a first sidewall insulating film formed at each side face of the first gate electrode; and
a first impurity diffusion region formed in a region of the semiconductor substrate which is located on each side of the first
gate electrode,
the second MIS transistor includes:
a second gate insulating film formed on the semiconductor substrate;
a second gate electrode formed on the second gate insulating film;
a second sidewall insulating film formed at each side face of the second gate electrode; and
a second impurity diffusion region formed in a region of the semiconductor substrate which is located on each side of the
second gate electrode, and
a first channel region is formed beneath the first gate insulting film so as not to be offset relative to the first impurity
diffusion region while a second channel region is formed beneath the second gate insulating film so as to be offset relative
to the second impurity diffusion region.
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