| US 7,468,533 B2 | ||
| Terraced film stack | ||
| Robert J. Hanson, Boise, Id. (US); Alex Schrinsky, Boise, Id. (US); and Terry McDaniel, Boise, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Mar. 27, 2007, as Appl. No. 11/691,770. | ||
| Application 11/691770 is a division of application No. 11/158220, filed on Jun. 21, 2005, granted, now 7,262,053. | ||
| Prior Publication US 2007/0187737 A1, Aug. 16, 2007 | ||
| Int. Cl. H01L 27/108 (2006.01) | ||
| U.S. Cl. 257—296 [257/605; 257/E27.084] | 21 Claims |
| 1. A memory device, comprising:
a substrate having a memory cell array area and a peripheral circuitry area, wherein the memory cell array area comprises
at least one polysilicon plug;
an insulating layer provided over the substrate;
at least one periphery contact defined in material layers over the substrate at the periphery circuitry area of the substrate,
wherein the material layers is at least the insulating layer, the peripheral contact having a low resistance metal film layer
provided over a portion of the insulating layer and forming metal silicide in contact with the substrate; and
at least one memory cell array contact defined in the material layers over the substrate at the memory cell array area of
the substrate, the at least one memory cell array contact having a terraced film stack with a metal mode film layer in contact
with the at least one polysilicon plug.
|