| US 7,468,530 B2 | ||
| Structure and method for failure analysis in a semiconductor device | ||
| Ki-Am Lee, Yongin-si (Korea, Republic of); Sang-Deok Kwon, Seoul (Korea, Republic of); and Jong-Hyun Lee, Suwon-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Nov. 30, 2005, as Appl. No. 11/291,242. | ||
| Claims priority of application No. 10-2004-0102543 (KR), filed on Dec. 07, 2004. | ||
| Prior Publication US 2006/0118784 A1, Jun. 08, 2006 | ||
| Int. Cl. H01L 29/74 (2006.01) | ||
| U.S. Cl. 257—207 [257/E21.521] | 27 Claims |
| 1. An analytic structure for semiconductor failure analysis, comprising:
a plurality of analytic fields disposed on a predetermined area of a semiconductor device;
semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array;
wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other
in a first direction; and
bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other
in a second direction,
wherein first and second analytic fields of the plurality of analytic fields each has a first layer comprising a first bitline
structure, and wherein the second analytic field has a second layer comprising a second bitline structure conductively coupled
to the first bitline structure of the first layer of the second analytic field, and wherein the first bitline structure of
the second analytic field is configured in a different pattern than the first bitline structure of the first analytic field.
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