US 7,468,299 B2
Non-volatile memory cells and methods of manufacturing the same
ChiaHua Ho, Kaohsiung (Taiwan); Erh-Kun Lai, Taichung County (Taiwan); and Hang-Ting Lue, Hsinchu (Taiwan)
Assigned to MACRONIX International Co., Ltd., Hsinchu (Taiwan)
Filed on Aug. 04, 2005, as Appl. No. 11/197,659.
Prior Publication US 2007/0031999 A1, Feb. 08, 2007
Int. Cl. H01L 21/336 (2006.01)
U.S. Cl. 438—259  [438/261; 257/E21.429] 21 Claims
OG exemplary drawing
 
1. A method comprising:
providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions;
forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and
forming a gate above the charge-trapping layer,
wherein the dielectric material is disposed in steps comprising: depositing a masking layer on a surface of the substrate; etching a pattern in the masking layer; and depositing the dielectric material in an area of the pattern in the masking layer.