a first module including a timing command generator configured to generate a command signal, the command signal related to a master clock signal;

a second module including a command interpreter configured to generate a timing reference signal related to the command signal and a local clock signal, wherein the second module includes a clock generator configured to receive the timing reference signal and the local clock signal and is configured to adjust a timing output of the second module so that the timing of the second module is synchronized to the master clock signal;

a counter configured to determine a number of pulses of the local clock signal that occur between a first pulse and second pulse of the timing reference signal;

an adder configured to determine a difference between the number of pulses of the local clock signal that occur between the first pulse and second pulse of the timing reference signal and a minimum number of local clock cycles to generate an ancillary (ADC) clock signal, the difference representing a number of excess local clock cycles;

a register configured to add the excess local clock cycles to the ancillary (ADC) clock signal and provide a first result; and

a comparator configured to compare the output of the register with a threshold value, wherein when the output of the register exceeds the threshold value, the comparator causes the ancillary (ADC) clock signal to be extended and causes the threshold value to be subtracted from the register, wherein any remainder in the register is applied to a subsequent ancillary (ADC) clock signal cycle.